Patents Examined by Jay Kim
  • Patent number: 9009840
    Abstract: In a resource-on-demand environment, virtual machine images are validated before use. A provider or source of a virtual machine image may generate a manifest, indicating executable components of the machine image. Before use, a created virtual machine may compare its executable components with those specified by the manifest. To ensure authenticity, the manifest may be associated with a signature, and the virtual machine may use the signature to verify the manifest and the source of the machine image.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 14, 2015
    Assignee: Amazon Technologies, Inc.
    Inventor: Thomas C. Stickle
  • Patent number: 7417673
    Abstract: The invention relates to photographing process, where zooming is carried out. In a method an image is formed through imaging optics onto a light sensitive image sensor in an imaging device and wherein the device is capable of both optical and digital zooming. The method comprises steps of determining an amount of available illumination, determining, according to the amount of available illumination, a ratio between the optical zooming and the digital zooming, and performing, according to which ratio, the optical and the digital zooming. The invention also relates to a device, controller, a computer executable program and a medium.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: August 26, 2008
    Assignee: Nokia Corporation
    Inventors: Antti Wright, Anne Juvonen, Ossi Kalevo
  • Patent number: 7411252
    Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: August 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Matthew J. Breitwisch, Edward J. Nowak
  • Patent number: 7405087
    Abstract: A magnetic memory device includes a first interconnection which runs in a first direction, a second interconnection which runs in a second direction different from the first direction, a magnetoresistive element which is arranged at the intersection of and between the first and second interconnections, and a metal layer which is connected to the magnetoresistive element and has a side surface that partially coincides with a side surface of the magnetoresistive element.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Nakajima, Keiji Hosotani
  • Patent number: 7397101
    Abstract: A horizontal germanium silicon heterostructure photodetector comprising a horizontal germanium p-i-n diode disposed over a horizontal parasitic silicon p-i-n diode uses silicon contacts for electrically coupling to the germanium p-i-n through the p-type doped and n-type doped regions in the silicon p-i-n without requiring direct physical contact to germanium material. The current invention may be optically coupled to on-chip and/or off-chip optical waveguide through end-fire or evanescent coupling. In some cases, the doping of the germanium p-type doped and/or n-type doped region may be accomplished based on out-diffusion of dopants in the doped silicon material of the underlying parasitic silicon p-i-n during high temperature steps in the fabrication process such as, the germanium deposition step(s), cyclic annealing, contact annealing and/or dopant activation.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: July 8, 2008
    Assignee: Luxtera, Inc.
    Inventors: Gianlorenzo Masini, Lawrence C. Gunn, III, Giovanni Capellini