Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation.

Abstract: An electronic device includes a memory device receiving a power supply voltage, a data strobe signal, and a data signal, and a system-on-chip that exchanges data with the memory device using the data strobe signal and the data signal. The system-on-chip performs write training that measures a magnitude of a delay of the data strobe signal due to variation in the level of the power supply voltage and adjusts a delay of the data signal using a result of the write training.

Abstract: The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform a program operation on a selected memory block among the plurality of memory blocks, and control logic configured to control the peripheral circuits to perform a retention acceleration operation including boosting a channel of a plurality of cell strings included in the selected memory block between a program voltage applying operation and a program verify operation during the program operation.

Abstract: A semiconductor device includes a first transistor; a first resistor; a second resistor; a first circuit configured to apply a first voltage to the first transistor. The first voltage is based on a difference between a reference voltage and an output voltage divided by the first and second resistors. A first current through the first circuit in a first mode is less than a second current through the first circuit in a second mode. The semiconductor device includes a capacitor connected to the output terminal; and a second circuit connected to the capacitor that: (a) disconnects the first circuit from the capacitor and apply a second voltage to the capacitor in a first mode, and (b) electrically connects the first circuit to the capacitor in the second mode.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A system and method of storing and reading digital data, including providing a nanopore polymer memory (NPM) device having at least one memory cell comprising at least two addition chambers each arranged to add a unique chemical construct (or codes) to a polymer (or DNA) string when the polymer enters the respective addition chamber, the data comprising a series of codes; successively steering the polymer from deblock chambers through the nanopore into the addition chambers to add codes to the polymer to create the digital data pattern on the polymer; and accurately controlling the bit rate of the polymer using a servo controller. The device may have loading chamber(s) to load (or remove) the polymer into/from the deblock chambers through at least one “micro-hole”. The cell may be part of a memory system that stores and retrieves “raw” data and allows for remote retrieval and conversion. The cell may store multi-bit data having a plurality of states for the codes.

Abstract: The present technology relates to an electronic device. A memory device configured to perform a sensing operation based on a charge degree of a sensing node includes a memory cell array including a plurality of memory cells, a peripheral circuit including a page buffer connected to a selected memory cell among the plurality of memory cells through a bit line, and configured to perform a sensing operation on the selected memory cell, and control logic configured to control the peripheral circuit to precharge a source line among lines connected to the memory cell array and perform the sensing operation based on a degree at which a sensing node in the page buffer is charged, during the sensing operation.

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

Abstract: In various embodiments, a memory cell arrangement is provided including a memory cell driver and one or more memory cells, wherein one or more control nodes of each of the one or more memory cells are electrically conductively connected to one or more output nodes of the memory cell driver. The memory cell driver may include: a first supply node to receive a first supply voltage and a second supply node to receive a second supply voltage, a plurality of input nodes to receive a plurality of input voltages, one or more output nodes, and a logic circuit connected to the first supply node, the second supply node, the plurality of input nodes, and the one or more output nodes, wherein the logic circuit includes one or more logic gates and is configured to connect via the one or more logic gates either the first supply node or the second supply node to the one or more output nodes in response to the plurality of input voltages.

Abstract: A memory device includes a common source line, a memory cell array, bit lines, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit lines are connected to the memory cell array. The conductive layer is formed over the bit lines. In an erase operation, the memory device increases a voltage of the bit lines to an erase voltage through capacitive coupling by increasing a voltage applied to the conductive layer.

Abstract: A memory device includes a memory cell array, a voltage switching circuit configured to switch a plurality of voltages provided to the memory cell array in response to a switching control signal, a discharge circuit configured to discharge the voltage switching circuit in response to a discharge signal, and a control circuit configured to generate the switching control signal based on a command and a high voltage enable signal received from outside of the memory device. The voltage switching circuit includes a high voltage switching circuit, and a low voltage switching circuit. The control circuit is configured to generate the discharge signal based on the command and an activated high voltage enable signal responsive to detecting external abortion while performing an operation corresponding to the command from among a program operation and an erase operation.

Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.

Abstract: A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

Abstract: A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. The processing unit then uses the sense amplifier and the accumulator to generate a first histogram of the set of data.

Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: Apparatuses, systems, and methods for voltage based random number generation. A memory may include a number of different voltages, which may be used to power various operations of the memory. During access operations to the memory, the voltage may vary, for example as word lines of the memory are accessed. The variability of the voltage may represent a source of randomness and unpredictability in the memory. A random number generator may provide a random number based on the voltage. For example, an analog to binary converter (ADC) may generate a binary number based on the voltage, and the random number may be based on the binary number.

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.