Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: A pipelined analog to digital converter comprises a first stage that receives an input voltage, that generates a first sampled digital value and a first residue voltage, and that includes a first amplifier that amplifies the first residue voltage and generates a first amplified residue voltage. A second stage receives the first amplified residue voltage, generates a second sampled digital value and a second residue voltage, and includes a second amplifier that amplifies the second residue voltage. At least one of the first amplifier and the second amplifier comprises a first transistor having a control terminal, a first terminal, and a second terminal, a transimpedance amplifier having an input that communicates with the first terminal of the first transistor, and an output, and an output amplifier having an input that communicates with the output of the transimpedance amplifier, and an output.

Abstract: A D/A conversion circuit in accordance with the present invention, which is provided with a switch swD, allows a writing operation of a voltage (a true gradation voltage) to be performed at a higher speed by first applying a first voltage (a voltage close to the true gradation voltage), which is supplied without passing through a resistor element, to an output line and then applying a second voltage (the true gradation voltage), which is supplied via the resistor element, to the output line. Thus, the present invention can provide a D/A conversion circuit capable of writing display data to liquid crystal cells with higher precision at higher speed, and a semiconductor device utilizing such a D/A conversion circuit.

Abstract: An apparatus for measuring energy usage. The apparatus can include an amplifier having a plurality of gain stages and the amplifier can be for receiving an input signal. The apparatus can also include an analog-to-digital converter that is coupled to the amplifier. Furthermore, the apparatus can include a scaling adjustment module that is coupled to the analog-to-digital converter. Additionally, the apparatus can include a gain control module coupled to the analog-to-digital converter.

Abstract: Systems, apparatus, and methods of encoding variable length data for efficient transport over a wireless channel. A wireless terminal can determine a frame size to encode, and can encode and transmit the frame data as one or more encoded blocks selected from a family of block sizes. Each block size can correspond to a particular encoder rate. The frame is parsed into a number of segments having a block size selected from the family of block sizes. The block sizes are selected to maximize the spectral efficiency of the frame. Each segment is then encoded with an encoder corresponding to the block size and having a coding rate that is configured to provide a substantially equal energy per symbol for all of the blocks. The encoded blocks are then aggregated and the smallest block zero padded. The aggregate of encoded blocks can be transported in one or more bursts.

Abstract: The invention relates to fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and one network of N comparators. The series resistor network receives a reference voltage and is traversed by a fixed current Io and the row i (i varying from 1 to N) comparator essentially comprises a dual differential amplifier with four inputs; two inputs receive a differential voltage VS?VN to be converted, a third being connected to a row i resistor of the network, and a fourth input being connected to an N-i row resistor of the network. The resistor network is supplied by a variable reference voltage originating from a servoloop circuit which locks the voltage level of the middle of the resistor network at a voltage equal to the common mode voltage (VS?VSN)/2 present at the output of the sample-and-hold module.

Abstract: A pipelined analog-to-digital converter (ADC) comprises a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC). The ADC includes an amplifier having an input and an output. N capacitances are connected in parallel and include first ends that selectively communicate with the input and second ends. N switches selectively connect the second ends of the N capacitances to the voltage input during a first phase, one of the second ends of the N capacitances to the output of the amplifier during a second phase, and others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase. A second stage communicates with the output the amplifier.

Abstract: A method of decompressing data words of an instruction set includes: A. filling a primary dictionary with at least one primary data word of the instruction set, each of the at least one primary data word being stored in the primary dictionary in a location associated with a distinct primary dictionary index; B. filling at least one secondary dictionary with at least one difference bit stream, each of the at least one difference bit stream being stored in one of the at least one secondary dictionary in a location associated with a distinct secondary dictionary index; C. receiving a code word, the code word comprising: a. a header which identifies the primary dictionary and a specific one of the at least one secondary dictionary; b. a first bit stream; and c. a second bit stream; wherein the first bit stream comprises the distinct primary dictionary index and the second bit stream comprises the distinct secondary dictionary index; D.

Abstract: Methods and systems that leverage the advantages of Huffman coding to increase processing efficiency of a data-stream while simultaneously minimizing storage requirements are provided. Decoding efficiency and table storage requirements can be balanced to produce systems that can be adapted for use in high-end network infrastructure applications and for low-resourced portable consumer devices. The systems and methods are operative in decoding data streams using multi-symbol codes and sign information, including AAC and MP3 data streams. A hierarchical structure of tables is described as having primary tables, secondary tables, tertiary tables and so on. Optimization balances processing requirements, table storage requirements and the described systems and methods may be implemented on a variety of processing platforms.

Abstract: In an optical coupled isolation circuit, a PWM encoder encodes a one-bit binary data signal supplied from a sigma-delta analog-digital converter in synchronization with a clock signal of a cycle T to produce a pulse width modulation signal. The pulse width modulation signal includes a narrower pulse having a width of 1/T and a wider pulse having a width of 3/T according to binary codes “0” and “1”. The pulse width modulation signal is transmitted to a decoder as a recovered pulse width modulation signal through a light emitting device, a light detector and an optical recovery circuit. A decoder decodes the recovered pulse width modulation signal at timing of a half of the clock cycle from each rising edge of the recovered pulse width modulation signal. The rising edge is synchronized with the clock signal. Thus, the clock signal and the data signal can be transmitted in one channel.

Abstract: N binary signals are transmitted through a bus of m leads, where m<n, at the rhythm of a train of clock pulses by encoding a first signal on a second signal. The encoding provides for the information associated with the first signal to be included in the second signal within a predetermined time interval of the clock period preceding each reading clock pulse. In this way one obtains a reduction of the switching activity on the bus and therefore a reduction of the energy consumption.

Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

Abstract: A Root Mean Square (RMS) detector circuit includes a first differential pair circuit arranged to operate in a common mode. The detector circuit also includes a compensation circuit unit having a second differential pair circuit to duplicate an unwanted base current drawn by the first differential pair circuit. The compensation circuit unit is arranged to generate an offset voltage using the duplicated base current. The compensation circuit unit also has an operational amplifier coupled to an NMOS transistor so as to generate a corrective current corresponding to the offset voltage, the corrective current being mirrored by a current mirror and provided as a compensatory current to an input of the first differential pair circuit.

Abstract: A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.

Abstract: Interleaved analog to digital converter with compensation for parameter mismatch among individual converters. A reference ADC samples an input signal at substantially the same time instances as an individual converter used in the interleaved ADC. The reference values provided by the reference ADC are compared with the digital codes generated by the converter to generate an error value from which estimates of the gain, DC offset and timing errors are computed using statistical techniques. Timing error thus estimated is used to change the phase of the sampling clock provided to the converter, and the gain and DC offset errors estimated are applied to modify the values of reference voltages applied to the converter, thus compensating for parameter mismatches.

Abstract: A circuit is provided to correct a sample rate by way of time domain interpolation having a first circuit loop having an up/down counter configured to receive an input signal and a feedback signal and an adder configured to receive the output signal from the up/down counter and to output a carry output as the feedback signal to the up/down counter and a second circuit loop configured to transmit a sum output from the adder to a modulator and to feed back an output signal from the modulator to an input of the adder.

Abstract: An image-decoding system with multi-run mechanism and method thereof are described. The image-decoding system with multi-run mechanism comprises IDLE, COEFF_READ, HUFF_ADDR_LOG, HUFF_ADDR_PHY, EOB_RUN_GEN, AMP_CAL, COEFF_WRITE state units. The IDLE state unit is used to reset a plurality of indicating signals to initial statuses, respectively. The COEFF_READ state unit coupled to the IDLE state unit can reads the data coefficients stored in a memory unit according to the indicating signals. The HUFF_ADDR_LOG state unit coupled to the COEFF_READ state unit locates a logical address of the data coefficients which is referred to the Huffman code to read the content of the data coefficients. The HUFF_ADDR_PHY state unit coupled to the HUFF_ADDR_LOG state unit can reads the data coefficients which are referred to the Huffman code stored in the memory unit to indicate a physical address of the data coefficients.

Abstract: A delta sigma modulator which employs a plurality of accumulators with non-power-of-2 modulus. The accumulators may consist of a primary non-power-of-2 modulus accumulator and a secondary non-power-of-2 modulus accumulator. The number of bits in the primary accumulators affects the frequency resolution of the resultant delta sigma fractional N frequency synthesizer and can be the minimum number of bits required by the resolution specification. The secondary accumulator integrates the carry outputs of its corresponding primary accumulators. This integration results in attenuating the dc content of the modulator output by a factor equal to the modulus of the secondary accumulators and may require compensation in the recombination block.

Abstract: Measurement data collected by isolated ADCs in multiple channels may be related. In such a scenario, data may be transmitted to a microcontroller or programmable logic device for centralized processing. Gain and offset of the ADCs in different channels, particularly their drift relative to one another, is an issue which requires attention. In particular, a pair of precision resistors is provided in calibrate the different channels. The ADCs may be factory calibrated and the ratio between the two precision resistors stored within the ADCs. The ADCs may later self-calibrate by comparing their relative gains to the stored resistor ratio. Gain of one of the ADCs may be adjusted relative to the other in order to maintain a relative gain calibration. Although absolute gain is not calibrated (as the resistors are isolated) for particular applications, only relative gain between the ADCs is relevant.

Abstract: Return-to-zero (RZ) formatted data is recovered and transmitted using non-return-to-zero (NRZ) devices. A NRZ clock and data recovery device (CDR) interprets the clock rate of a RZ formatted signal as twice its actual clock rate. Due to this interpretation, extra zeroes will be inserted in the data stream. The extra zeroes introduced by the NRZ interpretation of the data are discarded, and the interpreted clock rate is divided resulting in preserving the values of the original data stream of the RZ formatted signal. A NRZ encoded data stream at a specific clock rate is processed so that when the data stream is transmitted to a recipient expecting RZ formatted data, the recipient interprets the correct data.