Abstract: Techniques for virtual proxy based backup of virtual machines in a cluster environment are disclosed. In some embodiments, each of a subset of virtual machines hosted by physical nodes in a cluster environment is configured as a virtual proxy dedicated to backup operations. During backup, data rollover of each virtual machine in the cluster environment that is subjected to backup is performed using a virtual proxy.

Abstract: Disclosed herein is an apparatus and method for a key value store snapshot for a distributed memory object system.

Abstract: A flash memory storage device including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of well regions. Each of the well regions includes a plurality of memory blocks and a record block. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erase operation on the memory blocks of each of the well regions and record erase times of each of the well regions into the respective record block. In addition, a method for operating a flash memory storage device is also provided.

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: Embodiments of the present disclosure relate to a method, apparatus and computer program product for managing a data backup. The method comprises determining a first data amount to be involved in an addressing operation and a second data amount to be involved in a copy operation for an extent to be backed up on a source storage device, the addressing operation addressing a starting address of the extent and the copy operation copying an amount of data corresponding to a length of the extent. The method further comprises obtaining, based on an identifier of the source storage device, a first historical time elapsed for a previous addressing operation having the first data amount and a second historical time elapsed for a previous copy operation having the second data amount.

Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a buffer management circuit. The buffer memory includes an input buffer for storing input data received from a host and an output buffer for storing output data received from the memory device. The buffer management circuit changes capacities of the input buffer and the output buffer, based on a use state of at least one of the input buffer and the output buffer.

Abstract: The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.

Abstract: A computer system acquires information on a first present input subset selected from first present input data for a first step from a run-time log of the first step, determines whether or not first cache data corresponding to the first present input subset for the first step is present in a cache area with reference to management information, and determines the first cache data as present output data for the first present input data in a case where the first cache data is present.

Abstract: a memory system may include: a memory device including a plurality of memory blocks; and a controller configured to manage the plurality of memory blocks as a plurality of super blocks, the controller may classify and may manage super blocks formed by mixing and grouping at least one bad memory block and normal memory blocks as first super blocks, and may classify and may manage super blocks formed by grouping only normal memory blocks as second super blocks, the controller may check an accumulated size of write data received from a host, may group the write data into a plurality of data groups based on a result of the checking of the accumulated size, and may store, each time one data group is formed, the formed one data group in N first super blocks and M second super blocks.

Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag include: detecting, via a wireless memory host, a wireless memory tag; providing a vendor-agnostic command to the wireless memory tag to affect a change in a register-based interface of the wireless memory tag, wherein the change results in reading data from non-volatile memory of the wireless memory tag, writing data to the non-volatile memory of the wireless memory tag, or both.

Abstract: Some embodiments can include a system. In some embodiments, a system can comprise one or more processors and one or more non-transitory storage devices storing computing instructions configured to run on the one or more processors and perform acts.

Abstract: A storage system includes at least one drive chassis connected to at least one host computer via a first network, and a storage controller connected to the drive chassis, in which the storage controller instructs the drive chassis to create a logical volume, and the drive chassis creates a logical volume according to an instruction from the storage controller, provides a storage area of the storage system to the host computer, and receives an IO command from the host computer to the storage area of the storage system.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: Example peer storage systems, storage devices, and methods provide peer operation state indicators for managing peer-to-peer operations. Peer storage devices establish peer communication channels that communicate data among the peer storage devices that bypasses the storage control plane for managing the peer storage devices. The peer storage devices identify peer operations that communicate data through the peer communication channels and generate a peer operation state during the operating period of the peer operations. The peer storage devices activate a state indicator configured to indicate the peer operation state. The state indicator may be used to prevent a storage controller or other entity with access to the storage device, including administrative personnel, from performing an operation that may corrupt data or truncate a media operation involving peer-to-peer communications.

Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.

Abstract: In one aspect, runtime feature overhead minimization is provided for a storage system. An aspect includes providing a system table having features available to the system and a field indicating whether a feature is enabled. An aspect also includes providing a configuration table for data modules in the system that includes features available to storage units managed by the data modules and a field that indicates whether a feature is enabled for a storage unit. Upon receiving a request that includes a selected storage unit, the data modules access the system table. For each feature in the system table, the data modules determine whether the feature is set to enabled via the corresponding flag field. Upon determining the feature is set to disabled via the corresponding flag field in the system table, performing an operation identified in the request without accessing the configuration table.

Abstract: A method for implementing a shared memory buffer includes at an apparatus comprising a processor and a physical memory, running a host environment with a host virtual memory. The method further includes running a guest environment with a guest virtual memory, performing, by the host environment, an allocation of a frame buffer in the physical memory, and mapping the allocated frame buffer into the host virtual memory. Additionally, the method includes passing a handle of the allocated frame buffer to the guest environment and performing a mapping of the allocated frame buffer into the guest virtual memory, the mapping based on the handle of the allocated frame buffer.

Abstract: Apparatus and method for managing data in a multi-device data storage system. In some embodiments, a plurality of data storage devices are provided, each data storage device having a local driver circuit adapted to transfer data with a local memory module. A main driver circuit external to the plurality of data storage devices is configured to stream frequency modulated write data via parallel data transfer paths to the respective local driver circuits for concurrent transfer of the frequency modulated write data to the respective local memory modules.

Abstract: A processor core executes a first instruction indicating a first coherence state update policy that biases the cache memory to retain write authority, thereafter executes a second instruction indicating a second coherence state update policy that biases the cache memory to transfer write authority, and executes a store instruction following the first instruction in program order to generate a store request. A cache memory stores the cache line in association with a coherence state field set to a first modified coherence state. In response to the store request, the cache memory updates data of the cache line. If the store instruction is executed prior to the second instruction, the cache memory refrains from updating the coherence state field, but if the store instruction is executed after the second instruction, the cache memory updates the coherence state field from the first modified coherence state to a second modified coherence state.