Abstract: A method for accelerating recovery in a data replication environment includes maintaining a secondary out-of-sync bitmap for a secondary volume. The secondary out-of-sync bitmap indicates which storage elements on the secondary volume are not synchronized with storage elements on a primary volume. The method further generates, for the primary volume, a tracking bitmap indicating which storage elements on the primary volume need to be updated with data from the secondary volume. This tracking bitmap is initialized with values from the secondary out-of-sync bitmap. Upon receiving a write from the secondary volume to a storage element on the primary volume, the method resets the corresponding bit in the tracking bitmap. Upon receiving a write from a host system to a storage element on the primary volume, the method also resets the corresponding bit in the tracking bitmap. A corresponding system and computer program product are also disclosed.

Abstract: A method and associated systems for efficient management of cloned data. One or more processors create a “child” clone of a “parent” software image. The child and parent contain identical information organized into identical sets of file blocks. To conserve storage, each child block initially points to a physical storage location already in use by a corresponding parent block, rather than requiring additional storage of its own. The first time a child block is updated, however, it will require additional physical storage. At the time of the child's creation, the processors reserve a number of physical blocks sufficient to store the contents of all child file blocks likely to be updated. A child file block is identified as likely to be updated by analyzing past volatility of a corresponding file block of the parent or of corresponding file blocks of other children of the same parent.

Abstract: Methods, systems, and apparatus for allocating, by a source of one or more sources, a segment of a data file of a transient memory for exclusive access by the source, the transient memory being a distributed in-memory file system that supports remote direct memory access; writing, by the source, data from an initial partition to one or more blocks within the allocated segment of the data file, wherein a portion of the initial partition is written to a first block of the one or more blocks; publishing, by the source, the segment of the data file of the transient memory to be accessible for reading by one or more sinks; and reading by a particular sink of the one or more sinks, a particular block of the published segment of the data file of the transient memory, wherein the particular block is associated with the particular sink.

Abstract: Disclosed is an improved approach for implementing de-duplication, by selecting data such that the de-duplication efficacy of the storage will be increased without arbitrarily increasing metadata size.

Abstract: A plurality of storage apparatuses including a first and second storage apparatus, wherein said first storage apparatus is configured to have a first virtual volume composed of a plurality of virtual segments, at least said second storage apparatus is configured to have a pool composed of a plurality of real pages, each storage apparatus is configured to manage a virtual pool comprising one or more pools including at least said pool, said virtual pool is composed of a plurality of virtual pages, each virtual page corresponding to any real page, and said first storage apparatus is configured to receive a write command that specifies an address belonging to an unallocated virtual segment, allocate a free virtual page to said unallocated virtual segment, and write data to the real page corresponding to the allocated virtual page, even when said first storage apparatus does not have a pool composed of real pages.

Abstract: An image processing apparatus and control method are provided. An image processing apparatus including: a storage configured to store data which is divided into a plurality of units of code; a random access memory (RAM) configured to be loaded with the data; a central processing unit (CPU) configured to execute the data; and a storage controller configured to read a requested unit of code from the storage in response to receiving a request from the CPU for the unit of code to be currently executed, and load the read unit of code to the RAM so that the unit of code can be processed by the CPU, wherein the storage controller performs validation with regard to the unit of code when reading the unit of code from the storage, and loads the unit of code, when the validation passes, to the RAM.

Abstract: A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.

Abstract: A method and apparatus for capturing a snapshot of storage volumes of a data capture group are disclosed. In the method and apparatus, a request to create a data capture group may be received and processed. The data capture group may have one or more storage volumes. Upon defining the data capture group, a snapshot of the storage volumes of the data capture group may be taken.

Abstract: A processor includes a plurality of processing cores and a cache memory shared by the plurality of processing cores. The cache memory comprises a size engine that receives a respective request from each of the plurality of processing cores to perform an operation associated with the cache memory. The size engine fuses the respective requests from two or more of the plurality of processing cores into a fused request. To perform the fused request the size engine performs a single instance of the operation and notifies each of the two or more of the plurality of processing cores that its respective request has been completed when the single instance of the operation is complete.

Abstract: A method for accelerating recovery in a data replication environment includes maintaining a secondary out-of-sync bitmap for a secondary volume. The secondary out-of-sync bitmap indicates which storage elements on the secondary volume are not synchronized with storage elements on a primary volume. The method further generates, for the primary volume, a tracking bitmap indicating which storage elements on the primary volume need to be updated with data from the secondary volume. This tracking bitmap is initialized with values from the secondary out-of-sync bitmap. Upon receiving a write from the secondary volume to a storage element on the primary volume, the method resets the corresponding bit in the tracking bitmap. Upon receiving a write from a host system to a storage element on the primary volume, the method also resets the corresponding bit in the tracking bitmap. A corresponding system and computer program product are also disclosed.

Abstract: A memory device includes a plurality of NAND flash chips, a dynamic random access memory (DRAM) portion in data communication with the NAND flash chips, and a controller. Each NAND flash chip has a first storage capacity, and includes a memory section, each memory section including a plurality of pages. The DRAM portion has a second storage capacity that is at least as large as the first storage capacity. The controller is configured to select one of the NAND flash chips as a currently selected NAND flash chip for writing data, copy all valid pages in the currently selected NAND flash chip into the DRAM portion, and, in response to a write request to a logical memory location mapped to a particular physical location in one of the NAND flash chips, allocate the currently selected NAND flash chip for writing to a particular page that includes the particular physical location.

Abstract: Systems and methods are disclosed for estimating charge loss in solid-state memory devices using electrical sensors. A data storage device includes a solid-state non-volatile memory comprising a plurality of memory cells, a sensor configured to hold an electric charge, and a controller. The controller is configured to charge the sensor to a first charge level at a first point in time, determine a second charge level of the sensor at a second point in time, after a time period from the first point in time, and refresh data stored in the memory cells based at least in part on the determined second charge level.

Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

Abstract: An electronic device includes: a first non-volatile storage device, a second non-volatile storage device, and a processor. The first non-volatile storage device has limitations on a number of times of writing therein. The second non-volatile storage device has no limitations on a number of times of writing therein. The processor functions as: a normal writing section, a backup writing section, a substitute writing section, and a determination section. The normal writing section writes data into only the first non-volatile storage device. The backup writing section writes data into both the first non-volatile storage device and the second non-volatile storage device. The substitute writing section writes data into only the second non-volatile storage device. The determination section selects one of the normal writing section, the backup writing section, and the substitute writing section based on the number of bad blocks in the first non-volatile storage device.

Abstract: A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural process context identifiers to non-architectural local identifiers. The processor also includes a translation-lookaside buffer (TLB) having a plurality of address translations. For each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the non-architectural global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the non-architectural local identifiers to which the mapping module has mapped one of the process context identifiers.

Abstract: A system may include a plurality of memory cells and a processor. The plurality of memory cells may include a plurality of physical locations at which data is stored. The processor may be configured to determine whether to swap physical locations of data stored at logical block addresses in the first logical block address collection and physical locations of data stored at logical block addresses in the second logical block address collection. The processor may be further configured to, in response to determining to swap the physical locations of the data, swap the physical locations of the data stored at the logical block addresses in the first logical block address collection and the physical locations of the data stored at the logical block addresses in the second logical block address collection.

Abstract: A guarantee value setting unit stores therein a guarantee value of data send/receive performance with respect to a predetermined volume in a plurality of volumes held by a storage device. A bandwidth management unit calculates an interim target value on the basis of a comparison result between the guarantee value and an actual measurement value of the data send/receive performance with respect to the predetermined volume, allocates, on the basis of the interim target value, a bandwidth that compensates a difference between the guarantee value and the actual measurement value with respect to the predetermined storage area, and determines band distribution with respect to each of the volumes, and instructs the storage device to adjust the bandwidth in accordance with the determined band distribution.

Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support virtualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

Abstract: A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage space includes a plurality of buffer entries; providing a second storage space, wherein the second storage space includes a plurality of translation entries, and the translation entries correspond to a plurality of translation indices; and when receiving a write instruction to write a first virtual-to-physical address translation into a specific buffer entry of the buffer entries, storing the first virtual-to-physical address translation in a write translation entry of the translation entries according to a first part of bits of a first virtual address corresponding to the first virtual-to-physical address translation, and storing the first virtual address and a write translation index corresponding to the write translation entry in the specific buffer entry.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.