Abstract: A modulation apparatus includes: a modulation section that modulates, in accordance with a correlation table where a data sequence with a predetermined number of bits is associated with a code sequence with a predetermined number of bits, the data sequence into the code sequence to allow a predetermined demodulation section to demodulate the code sequence into the data sequence in accordance with the correlation table, wherein the code sequence is, on NRZI method, a MSN code sequence where a null point of a frequency spectrum on a recording channel or communication channel of the code sequence is matched with a null point of a frequency spectrum of a PR equalized signal including the code sequence and a minimum run length is limited to be greater or equal to one.

Abstract: A mobile terminal device includes a detector, a transceiver, an analyzer, an execution module, and a connection module. The detector generates a probing request signal. The transceiver receives signals sent from a plurality of access points (AP). The analyzer retrieves a plurality of Received signal strength Indications (RSSI) of the plurality of APs and workload of the plurality of APs by analyzing the signals. The execution module generates a plurality of indices of the plurality of APs based on an analysis results, and selects one of the plurality of indices as a best comprehensive index. The connection module establishes a connection between an AP corresponding to the best comprehensive index and the mobile terminal device.

Abstract: A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

Abstract: A method for testing a digital to analog converter, which operates in an undersampling environment, wherein signals of a tested DAC and a signal generator are modulated by a PWM device and then processed by a digital processing circuit to generate a digital signal, whereby is formed a low-speed equivalent ADC. The signal generator is provided by uniform-distribution random test patterns, and the signal generator generates an uniform-distribution random analog signal to the equivalent ADC. Thereby, the test error caused by the non-ideality of the signal generator is corrected, and the tested circuit can work in a full speed.

Abstract: A parallel-to-serial conversion circuit for converting pieces of parallel data into serial data, and a parallel-to-serial converting method thereof include: a shifter configured to sequentially shift an initiation signal to generate a plurality of transfer activation signals; a valid duration generator configured to define valid durations of the plurality of pieces of parallel data based on a clock and the plurality of transfer activation signals; and an output unit configured to receive the plurality of pieces of parallel data whose valid duration has been defined and to drive an output in response to a piece of data from among the received parallel data whose valid duration has begun.

Abstract: A track-and-hold circuit includes a first sampling circuit that samples an analog input signal, a second sampling circuit that samples the analog input signal, the second sampling circuit and the first sampling circuit being connected in parallel, a first amplifier that amplifies a signal output from the first sampling circuit, and a second amplifier that amplifies a signal output from the second sampling circuit.

Abstract: A method for encoding a message communicated between devices, the message having at least one field, the method comprising: if the field is not optional and contains a value, writing the value to one or more data bytes in a byte buffer; and, if the field is optional and contains a default value, marking a bit in a reserved byte in the byte buffer to indicate that the field contains a default value.

Abstract: A decoder device has a reference voltage generating section for outputting first and second threshold level signals, a first comparator for comparing a stair-stepped waveform input signal and the first threshold level signal to output a comparison result, a second comparator for comparing the input signal and the second threshold level signal to output a comparison result, and a logical operation section for performing a logical operation between output signals of the first and second comparators to output a signal decoded from the input signal. A threshold level represented by the first threshold level signal intersects a riser section of one stepped waveform out of two adjacent stepped waveforms in the input signal, and a threshold level represented by the second threshold level signal intersects a riser section of the other stepped waveform out of the two adjacent stepped waveforms of the stair-stepped waveform input signal.

Abstract: According to embodiments of the present technique, a system and a method for obtaining low-noise measurements for a wide range of analog signal strengths is provided. According to aspects of the present technique, a low-gain measurement of an input pixel charge is performed, wherein the input pixel charge is distributed to two feedback capacitors, which together provide a relatively low integrator gain. After the low-gain measurement, a high-gain measurement is performed, wherein one of the capacitors is remove from the feedback loop and the charge is redistributed to the remaining capacitor.

Abstract: A sampling circuit includes multiple sampling channels adapted to sample the signal in time-multiplexed fashion. Each sampling channel includes a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. In an embodiment, the holding time period includes a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.

Abstract: A digital-to-analog converter generates a voltage from power supply and ground voltages, generates upper and lower limit reference voltages for a reference width which regards the generated voltage as an intermediate potential, converts a change in an analog input signal with respect to the upper and lower limit reference voltages into a digital code, and performs a control in order to achieve a sample and hold of the analog input signal.

Abstract: A digitizer includes an analog to digital converter (ADC), a sampling frequency generator, and a controller. The ADC samples an IF signal to generate a digital signal. The sampling frequency generator is connected to the ADC and provides a sampling clock of variable frequency to the ADC. The controller is connected to the sampling frequency generator and determines frequency of the sampling clock.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: A method and system for sampling values. Multiple values are sampled concurrently. One of the values is stored while another one of the values is converted to a corresponding digital value by an analog-to-digital converter (ADC). Subsequently, the stored value is made available to the ADC.

Abstract: A signal processing device, even when a steep difference in DC level is included in a signal read from a disc such as a DVD-RAM format, cuts off the DC level and pulls the read signal into an appropriate A/D input level. A steep difference in DC level between a data section and a CAPA section is absorbed by a first offset unit, and an asymmetry which occurs due to variations in the disc manufacturing stage is corrected by a second offset unit. Further, a control signal for operating the two offset units exclusively is generated by a controller, thereby controlling both offset units.

Abstract: According to an embodiment of the present invention, a data encoding method includes separating an input sequence into a plurality of n-bit blocks, wherein n is a natural number, and converting each of the n-bit blocks into a block code including M rows and N columns such that every bit in the block code has at least one identical bit adjacent horizontally or vertically to the bit, wherein M and N are natural numbers.

Abstract: Methods and systems for mitigating latency in a data detector feedback loop are included. For example, a method for reducing latency in an error corrected data retrieval system is included. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.

Abstract: A gain circuit comprises a main amplification unit and a first refresh unit. The main amplification unit comprises an amplifier, a first capacitor connected between a first input terminal of the gain circuit and a first input terminal of the amplifier, and a second capacitor connected between the first input terminal of the amplifier and a first output terminal of the amplifier. The first refresh unit comprises a first capacitor connected with a first terminal of the first capacitor to a common node of the first refresh unit, and a second capacitor connected with a first terminal of the second capacitor to the common node of the first refresh unit. The common node of the first refresh circuit is arranged to be supplied with a reference voltage (Vref, Vcm,ref) during a first phase of a refresh interval and connected to the first input terminal of the amplifier during a second phase of the refresh interval.

Abstract: A device for generating an electrical signal with a wide band arbitrary waveform includes at least two continuous wave lasers each being adapted to produce light at a different wavelength. The device also includes at least one pulse generator adapted to convert the light from the lasers into optical pulse trains and a plurality of optical modulators. Each modulator is adapted to receive an optical pulse train at at least one wavelength and modulate the optical pulse train in response to an electromagnetic signal. An optically dispersive element is adapted to receive the optical pulse trains from the modulators and to introduce a wavelength dependent delay between the optical pulse trains. The device further includes a photodetector for receiving the modulated dispersed optical pulse trains and producing an analogue electrical signal in response thereto.