Abstract: A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches to select a proper termination chip for the computer system bus. The apparatus includes one or more multi-sided termination boards with etched leads, lands and feed-throughs. The termination chips may be mounted on either one side, or both sides of each board. Connection between the termination boards and the mother board are made by means of a comb of contact fingers or edge-connector which mates with a connector on the mother board. The data lines and address lines of the computer bus are distinct from each other, and routed to the termination board via the edge connector. A set of CMOS TTL or FET switches are located adjacent to the comb, and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU, controller or other decoding means located on the motherboard.