Abstract: A desktop computer system having the capability to suspend and resume the state of the computer system. The suspended system state is saved to the system hard file such that system power may be removed, effectively allowing a system suspend requiring no power from the power supply.

Abstract: A magnetic disk apparatus which is used as a subsystem of a computer system, in particular a medium-sized computer system which uses commercial power and does not have its own backup power, provided with a plurality of directors (118), a plurality of magnetic disk modules (148) commonly accessed from the plurality of directors, a plurality of director batteries (114-m) for supplying power individually to the plurality of directors, magnetic disk module batteries (114-n) for supplying power to the magnetic disk modules, and a power controller (110) for independently controlling the supply of power from the plurality of director batteries and magnetic disk module batteries in accordance with the operating state of the plurality of directors and magnetic disk modules. (FIG. 1).

Abstract: A logic LSI chip includes a CPU, a bus, a memory, and a multiplier. In addition, the logic LSI chip includes a command signal line for transferring, from the CPU to the multiplier, a command regarding a multiplication instruction relating to data read out, while the data is being read out from the memory, so that the multiplier can fetch the data directly from the bus. While the CPU is reading data from the memory, therefore, a command of a multiplication instruction relating to data read out is transferred from the CPU to the multiplier. A bus cycle control circuit receives a state signal from the multiplier when the multiplier is executing a repetitional operation and the bus cycle control circuit responds to the state signal by signalling the CPU to delay issuance of a succeeding command to the multiplier.

Abstract: A method for transferring data through a bus bridge. The bus bridge includes a number of data buffers for storing data, prefetching data and write posting data. A device communicating with the bus bridge may reserve a buffer by one of two reservation mechanism. The reservation mechanism provides the bus bridge with the address and byte count. The reservation may also be forwarded to any upstream bus bridges. The reserved buffers are prefetched for efficient use of bus access. Data is prefetched and flushed according to alternative algorithms if a buffer is not reserved.

Abstract: An interrupt process distributing system, provided in a CPU board in a loose-coupled type multiprocessor system formed of a plurality of CPU boards and one I/O board which are interconnected through common mediation and interrupt busses. A CPU executes interrupt requests; a queue counter, connected to the CPU through an internal bus, counts the interrupt requests which are sent from the common bus to and queued in the CPU. An interrupt transfer control unit, connected to the CPU and the queue counter through the internal bus, counts the interrupt requests as received from the interrupt bus, compares the number of queued interrupts with the number of received interrupt requests, and transfers the received interrupt requests to the CPU when the number of the received interrupt requests exceeds the number of queued interrupt requests.

Abstract: A control circuit for the interface circuit of a module of a distributed process control system permits its kernel submodule and peripheral submodule to communicate through the interface circuit notwithstanding that the structure and protocol of module BUS of the kernel submodules is incompatible with the structure and protocol of the PCI BUS of the peripheral submodule. The control circuit includes a module BUS state machine (MBSM), a PCI target state machine (PTSM), an arbiter state machine (ARSM), and an address decode logic (ADL) circuit. In response to control signals from the kernel and peripheral submodules applied to the control circuit over their respective buses, and control signals produced by the MBSM, the PTSM, the ARSM, and the ADL circuit. Which one of the two submodules is granted access to the registers of the interface circuit is determined by the control circuit which also grants the peripheral submodule access through the interface circuit to the memory of the kernel submodule.

Abstract: A scheme for supporting cooperative works capable of reproducing the contents of the past works from the recorded history of the cooperative works accurately, such that the cooperative works can be carried out efficiently and smoothly. In this scheme, the inputs made by each user during the cooperative works are stored in correspondence to input target data indicating input target applications of the inputs as a record of the cooperative works. Then, afterwards, the input target applications indicated by the input target data are re-executed according to the stored inputs to reproduce results of the cooperative works resulting from the inputs which can be presented to each user.

Abstract: An adapter for transferring blocks of data of a variable size to at least one destination adapter, each of the adapters being plugged in a respective slot and connected to a main system bus which is controlled by a central backplane card. In each adapter, the transmission of one block of data is provided, in part, by a device, operative in response to the detection of an ACK acknowledge word giving access to the bus, for generating a signalling word to be transmitted to a particular destination adapter which will actually receive the transmitted data; the signalling word comprising information characterizing the type of command which the transmitting adapter sends as a request to the backplane card, the address of the particular adapter which will receive the transmitted data, the size of the block of the transmitted data and the address of the transmitting adapter. The adapter is best suited for use in multimedia systems where variable size data blocks are required to transmit data, voice, video, etc.

Abstract: A notebook computer (10) includes provides power to a parallel port floppy drive (24) through the parallel port connector (48). The computer (10) includes a power switching circuit (30) which detects whether a printer or floppy drive is connected to the parallel port connector (48). If a floppy drive (24) is connected, the power is enabled through the parallel port connector (48). If a printer is connected, power is disabled through the parallel port connector (48).

Abstract: A system and method for recovering from a power failure in a digital camera comprises a power manager for detecting power failures, an interrupt handler for responsively incrementing a counter device, service routines which register to receive notification of the power failure, and a processor for evaluating the counter and providing notification of the power failure to the service routines which then assist the digital camera to recover from the power failure.

Abstract: A computer system and method for performing data transfers during idle PCI clock cycles. The computer system includes a PCI bus, a plurality of devices coupled to the bus, and a bus arbiter coupled to the bus. One of the plurality of devices is a source device, such as a CD-ROM drive controller, and one of the plurality of devices is a destination device, such as an MPEG video decoder. The system further includes a source ready signal, a destination ready signal and an idle acknowledge signal each coupled to the bus arbiter, the source device and the destination device. The source device asserts the source ready signal when the source device is ready to send data to the destination device. The destination device asserts the destination ready signal when the destination device is ready to receive data from the source device. The bus arbiter asserts the idle acknowledge signal when each of the plurality of bus request signal and bus grant signal pairs is deasserted and the bus is idle.

Abstract: A distributed computer system having a plurality of end user terminals and a plurality of loosely coupled server computers that share no resources with each other. A multiplicity of user application processes are distributed over the server computers. An Enq table is stored on a first one of the server computers. The Enq table includes Enq records, each representing a locked resource. When any user application process executes an Enq instruction naming a specific resource, if the Enq table does not already contain an Enq record for the specific resource an Enq record is generated and stored in the Enq table representing the specific resource as locked. The Enq record is stored in the same Enq table on the first server computer regardless of which server computer executes the Enq instruction. If the Enq table does already contain an Enq record for the specific resource, execution of the user application process that executed the Enq instruction is suspended.

Abstract: A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a first bidirectional signal line, a second bidirectional signal line coupled to the bus clock and data lines, respectively, and an interface circuit coupled to the first and second bidirectional signal lines. The interface circuit includes a first buffer circuit coupled to the first and second bidirectional signal lines, and a second buffer circuit coupled to the first buffer circuit.

Abstract: In accordance with the teachings of this invention, a novel voltage regulator is taught which is capable of being formed solely of MOS devices. This eliminates the need to utilize off chip components to form a stand-alone voltage regulator, and avoid the process complexities and increased cost associated with BICMOS fabrication processes.

Abstract: A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.

Abstract: An aircraft control system improves system flexibility, scalability, redundancy, and separation. The system uses a "virtual backplane" architecture which maximizes system flexibility and scalability and allows easy integration of new functions. The architecture comprises four major elements: processing modules; input and output modules (i.e. I/O modules); database modules; and an aircraft wide system network. Inter module communication occurs via the aircraft wide system network thereby eliminating the need for point to point communication and making modules independent of physical location or what modular units (MUs) they are in. Predetermined periodic and deterministic broadcast techniques improve the safety and communications efficiency of the system.

Abstract: Disclosed is an apparatus capable of supporting a variety of optional extension modules for a portable computer, comprising a port connector for connecting any of the optional extension modules; and a selector for receiving a control signal from the connected module through the port connector and enabling the portable computer to communicate with the connected module. With the module supporting apparatus, a variety of optional extension modules can be connected to the computer by using the port connector. Besides basic functions, the portable computer can perform a variety of functions, such as a multi-media function, etc.

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.

Abstract: A PCI local processing system is operated at 50 MHz using 5 V connectors for add-in boards and a 5 V signaling environment with an appropriate timing budget. Only the 5 V add-in boards may be used for 50 MHz adapters installed in the bus. The bus is backward compatible with existing 33 MHz PCI specifications and operates at 33 MHz if a 33 MHz adapter is installed, and will operate at 50 MHz if only 50 MHz adapters and/or 66 MHz adapters which utilize the universal boards are installed.

Abstract: Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in a CPU 1 of 8 bits so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU.The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU.