Abstract: A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access memories; circuits including a control circuit which is coupled with the nonvolatile memory and the synchronous dynamic random access memories, and controls accesses to the nonvolatile memory and the synchronous dynamic random access memories; and a plurality of input/output terminals coupled with the circuits, wherein in data transfer from the nonvolatile memory to the synchronous dynamic random access memories, error corrected data is transferred.

Abstract: Methods and systems for managing disk capacity allocated to a data log in a source data storage system during a merge process are disclosed. Data in the data log may be merged into corresponding data on a destination storage system connected to the source data storage system by at least one communication link. In one embodiment a method comprises maintaining a ratio of merge writes out of the data log to writes from a host computer into the data log within a desired range until the write process reaches a predetermined distance from the end of the data log, and quiescing writes from a host computer into the data log until the data log is fully written to the destination storage system.

Abstract: A system is described in which a plurality of host computers are coupled to a storage system for storing and retrieving data in the storage system. The storage system includes individually addressable units of storage such as volumes or logical unit numbers. A security management system controls access to each of the individually addressable units of storage based upon the identification of the host permitted to access that unit of storage.

Abstract: A system is described in which a plurality of host computers are coupled to a storage system for storing and retrieving data in the storage system. The storage system includes individually addressable units of storage such as volumes or logical unit numbers. A security management system controls access to each of the individually addressable units of storage based upon the identification of the host permitted to access that unit of storage.

Abstract: An address calculation unit calculates a plurality of addresses corresponding to a plurality of data included in a data packet. A first bank memory access unit accesses a first bank memory according to a first address calculated by the address calculation unit. Simultaneously, a second bank memory access unit accesses a second bank memory according to a second address calculated by the address calculation unit. A packet reconstruction unit reconstructs the data packet according to the results of access by the first and second bank memory access units. Accordingly the processing rate of the data packet including a plurality of data is increased.

Abstract: In a disk-based data storage system, a controller configured to control a reference count regeneration operation, the controller includes a control register, an address register, a status register, a boundary register, and an embedded memory. The control register may be configured to set up and initiate program instructions that are executed by at least one processor. The address register may be configured as a cache address pointer and correspond to at least one of a sort output list pointer, a virtual track table input list pointer, a reference list pointer, a track number table pointer, and a reference count mis-compare list pointer. The status register may be configured to indicate status of a routine. The routine includes at least one of a radix sort, a reference list count, a combine counts, and a merger of the reference list count into the TNT to generate an updated TNT.

Abstract: There is provided a storage system suitable for an open system which has advanced security functions for logical devices. In a storage system such as a RAID system, 6 types of access attributes which are Readable/Writable, Read Only, Unreadable/Unwritable, Read Capacity 0, Inquiry Restricted, and S-vol Disable, can be set for each logical device. Read Capacity 0 makes a response “capacity 0” upon inquiries from hosts about capacity. Inquiry Restricted does not permit the hosts to recognize logical devices. S-vol Disable does not permit pair forming for duplication of a logical device with another device as the destination of copying. Upon receipt of commands from hosts of the open system, the storage system changes command processes and responses, depending on the difference in operation system, vendor, version, or the like, between hosts.

Abstract: The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and application parameters. The cache parameters include a cache size, cache line size, set associativity, address-to-cache-line mapping algorithm, and set replacement algorithm. The optimization parameters specify the minimum acceptable efficiency level. The application parameters include a list of object modules and functions within those modules. All possible orderings of the modules are stepped through to determine where the specified functions fall within the cache given the location of the function within the module. The function locations in each permutation of the orderings are analyzed to find a solution that matches or beats the optimization parameters. In an embodiment, a front-end analysis program (“tool”) and a back-end processing stage, usually related to a linker, are provided.

Abstract: A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.

Abstract: A first data transfer module sends update data to be written into a primary volume to a second data transfer module; the second data transfer module stores the update data into a secondary volume, stores differential data written to a storage address for the update data in the secondary volume into a second differential volume, updates a second management information holding module, and then informs completion of the data updating to the first data transfer module; and the first data transfer module stores the update data to an update address in the primary volume when the information of completion of the data updating is received from the second data transfer module, stores the differential data into a first differential volume, and updates a first management information holding module.

Abstract: A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists between a first read request to the first bank and a second read request to the first bank, a first write request is executed to the second bank during a delay. The delay takes place after the first read request is executed and before the second read request is executed.

Abstract: Asynchronous memory devices utilize loopback circuitry to provide efficient and high speed “flow-through” of write data when conventional flow-through operations are not available. An exemplary memory device includes a memory array having first and second ports that can each support asynchronous read and write access and a first input/output control circuit. The first input/output control circuit is electrically coupled to the first port and includes a first sense amplifier, which is configured to receive read data from the first port, and a first bypass latch having an output coupled to the first sense amplifier. A second input/output control circuit is also provided. The second input/output control circuit is electrically coupled to the second port and includes a second sense amplifier, which is configured to receive read data from the second port, and a second bypass latch.

Abstract: An address translation manager creates a set of chained tables that may be allocated in non-contiguous physical memory, and that may be dynamically resized as needed. The chained tables comprise one or more tables that each correspond to a logical partition, with each table including a pointer to a table corresponding to a virtual connection in the logical partition. The chained tables are managed by the address translation manager, which uses the system memory manager to dynamically allocate and free memory for a chained table as needed.

Abstract: A storage system 1 includes: plural protocol transformation units 10 that transform, to a protocol within the system, a read/write protocol of data exchanged with servers 3 or hard disk groups 2; plural cache control units 21 that include cache memory units 111 storing data read/written with the servers 3 or the hard disk groups 2 and which include the function of controlling the cache memory units 111; and an interconnection network 31 that connects the protocol transformation units 10 and the cache control units 21. In this storage system 1, the plural cache control units 21 are divided into plural control clusters 70, control of the cache memory units 111 is independent inside the control clusters, and a system management unit 60 that manages, as a single system, the plural protocol transformation units 10 and the plural control clusters 70 is connected to the interconnection network 30.

Abstract: Methods and structure for initializing a RAID storage volume substantially in parallel with processing of host generated I/O requests. Initialization of a RAID volume may be performed as a background task in one aspect of the invention while host generated I/O requests proceed in parallel with the initialization. The initialization may preferably the performed by zeroing all data including parity for each stripe to thereby make each stripe XOR consistent. Host generated I/O requests to write information on the volume may utilize standard read-modify-write requests where the entire I/O request affects information in a portion of the volume already initialized by background processing. Other host I/O requests use standard techniques for generating parity for all stripes affected by the write requests. These and other features and aspects of the present invention make a newly defined RAID volume available for host processing is quickly as possible.

Abstract: A network services processor receives, stores, and modifies incoming packets and transmits them to their intended destination. The network services processor stores packets as buffers in main and cache memory for manipulation and retrieval. A memory subsystem stores packets as linked lists of buffers. Each bank of memory includes a separate memory management controller for controlling accesses to the memory bank. The memory management controllers, a cache management unit, and free list manager shift the scheduling of read and write operations to maximize overall system throughput. For each packet, packet context registers are assigned, including a packet handle that points to the location in memory of the packet buffer. The contents of individual packets can be accessed through the use of encapsulation pointer registers that are directed towards particular offsets within a packet, such as the beginning of different protocol layers within the packet.

Abstract: By the same method as that of making data access to a data storage area in an online state, it is performed to access a data storage area other than the data storage area. A plurality of logical volumes carried by a disk array apparatus includes an online volume that is in an online state to a host and an offline state that is in an offline state to the host. The host transmits an access command including target information designating a target volume to the disk array apparatus as an access command to a starting volume other than the target volume. The disk array apparatus receives the access command to the starting volume and offers the data access to the target volume on the basis of the target information carried by that access command to the host.

Abstract: A method for automatically (i.e., programmatically) determining a storage configuration for a storage system for a given application. The method may receive information on existing storage capabilities in the storage system and information regarding the software application that will use the storage system. The method may then automatically determine a storage configuration for the storage system based on the existing storage capabilities in the storage system, the information regarding the application, and application specific rules about storage configuration principles of the application. The rule may comprise priority information that specifies a priority in application of the rules, e.g., a structure or list of storage types in order of priority for different application data types.

Abstract: A memory architecture with a multiple cache coherency includes at least one processor with a storage area in communication with a cache memory. A main bus transmits and receives data to and from the cache memory and the processor. A coherency control in communication with the cache memory and the processor is configured to determine an existence or location of data in the cache memory or the storage area in response to a data request from the main bus. The coherency control dispatches an existence or location result to the main bus.

Abstract: Methods and systems for managing disk capacity allocated to a data log in a source data storage system during a merge process are disclosed. Data in the data log may be merged into corresponding data on a destination storage system connected to the source data storage system by at least one communication link. In one embodiment a method comprises maintaining a ratio of merge writes out of the data log to writes from a host computer into the data log within a desired range until the write process reaches a predetermined distance from the end of the data log, and quiescing writes from a host computer into the data log until the data log is fully written to the destination storage system.