Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

Abstract: A method of encapsulating a semiconductor device comprising the steps of providing a mold having top and bottom halves each with cavities for holding semiconductor devices, and further having gates and runners for feeding encapsulation material into said cavities; lining said cavities with protective plastic films; providing a plurality of semiconductor integrated circuit chips, each having an outline; providing an electrically insulating interposer; assembling said chip and said interposer, loading said assembly into said mold and introducing into said mold a low-viscosity, high adhesion encapsulation material; at least partially curing said encapsulation material, thereby forming a flat, high-luster surface; opening said mold and removing said interposer together with said encapsulated chips from said mold; attaching an array of solder balls to the exposed surface of said interposer; and singulating said encapsulated semiconductor devices, thereby forming devices having an outline substantially the same as

Abstract: A semiconductor device is provided with a semiconductor chip and a connection lead connected to a pad of the semiconductor chip. The connection lead has a tip part which is bent up to a surface of the semiconductor chip on the opposite side of the pad. The semiconductor device is further provided a resin sealed part covering the semiconductor chip and a solder ball provided on the tip part of the connection lead.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: The semiconductor device includes a semiconductor chip and tapes. The tape includes insulating layers with the conductive layers which are sandwiched between the insulating layers. The tapes extend from the front surface to the back surface of the semiconductor chip and are fixed to the chip. Each of the conductive layers is exposed at the front and the back sides of the chip, respectively.

Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

Abstract: A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts.

Abstract: A composite wiring structure (10) for use with at least one semiconductor device (16). The composite wiring structure having a first conductive member (12) upon which the semiconductor device can be mounted for electrical connection thereto. A dielectric member (20), made of ceramic or organo-ceramic composite material, is bonded to the first conductive member (12) and contains embedded therein a conductive network (24) and a thermal distribution network (26). A second conductive member (32) may be incorporated with the composite wiring structure, with a capacitor (64) being electrically connected between the conductive network (24) and the second conductive member (32). Bonding between the dielectric member and the conductive members may be in the form of a direct covalent bond formed at a temperature insufficient to adversely effect the structural integrity of the conductive network and the thermal distribution network.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

Abstract: A semiconductor element has electrodes on its periphery, leads for making external connections respectively in correspondence with the electrodes and connected to the electrodes through wires, and a package body in which a semiconductor element and leads are encapsulated with a resin material. The leads extend toward the bottom side of the package body for insertion into a socket and are bent alternately in a raised shape and a recessed shape, with the tops of the raised parts and the bottoms of the recessed parts exposed at side surfaces of the package body. The parts serving as the external connection electrodes (i.e., the tops of the raised parts and the bottoms of the recessed parts) are arranged at a large pitch, so that the area of the external connection electrodes can be enlarged to enhance the reliability of the contact.

Abstract: A semiconductor device includes a semiconductor layer, prelayer, refractory layer, and conductive layer. The conductive layer includes an ohmic contact layer, and may also include a barrier layer, of a highly stable, low-resistance element or compound, such as Au or Ti, which is formed on the refractory layer. The refractory layer is a material that does not react with, or dissociate from, either the prelayer or the conductive layer when the semiconductor device is exposed to relatively high temperatures. The refractory layer material may be metal suicides, phosphides, or nitrides. The material of the prelayer is selected to minimize strain between the prelayer, the refractory layer and the semiconductor layer to provide a relatively strong bond between the refractory layer and semiconductor. The prelayer may be selected to provide relatively high current injection to the semiconductor, and may further form a low Schottky barrier height with the semiconductor.

Abstract: The present invention provides a semiconductor package, the package comprising: a base substrate having a perforation formed therein, the perforation including a bottom and the base substrate including a backface; an electrode portion secured to the backface of the base substrate and disposed on the bottom of the perforation; a semiconductor device electrically connected to the electrode portion and disposed on the backface of the base substrate; a sheet elastic body interposed between the semiconductor device and the electrode portion; and leveling means between the sheet elastic body and the electrode portion for eliminating gaps along the electrode portion. In the semiconductor package neither deformation nor cracks of the package will be produced even if heat history is applied during packaging and the package density can be improved. The present invention further provides a process for the production of the semiconductor package.

Abstract: A plug structure capable of directly coupling to a packageless bonding pad without having to go through a third conductive medium. The plug structure includes several plugs on a base substrate, such as a printed circuit board or a carrier. A solder is disposed on the plug surface in which the plug can be a cylinder or mushroom-like shape and the solder can be a film or a ball.

Abstract: In one version, a PC card has a printed circuit board assembly (11) that is interposed between card shields (5,6). This PC card is frameless. In another version, a PC card has: card shields (103,104); a printed circuit board assembly (110) interposed between the card shields; and two interposing side frames (105, 105′).

Abstract: A semiconductor chip is bonded on a radiator plate consisting of copper material with interposition of a bonding layer having a total thickness of 80 &mgr;m comprising a laminated structure including a thermoplastic film bonding layer 12a having a thickness of 50 &mgr;m and a paste-based bonding layer 12b having a thickness of 30 &mgr;m. For example, butadiene-modified polyolefin-based adhesive resin mixed with alumina fine power is used as material of the thermoplastic film bonding layer 12a, and, for example, silicone rubber-modified epoxy-based adhesive resin mixed with silver powder is used as material of the paste-based bonding layer 12b. There is thus provided a semiconductor device having a semiconductor chip bonded on a radiator plate with interposition of a bonding layer, wherein stress concentration caused in the bonding layer is relaxed and heat dissipation performance is maintained and thus the reliability in endurance is high, and a method for manufacturing the semiconductor device.

Abstract: Package embodiments for integrated circuits or other electronic devices are disclosed, along with methods of making and interconnecting the packages. The packages include a package body formed of molded encapsulant. Leads extend from a first end that is embedded at a lower surface of the package body second end that is outside the package body. The leads are bent up the sides of the package and over the top surface of the package. The packages have mounting keys so that a plurality of packages may be precisely stacked one on top of the other. Abutting leads of the stacked packages may be electrically interconnected. The packages also may be placed next to each other so that their leads abut and may be electrically interconnected.

Abstract: A semiconductor device having one or more semiconductor chips and chip components and a manufacturing method. In the semiconductor device, electrical short of the chip components and the like can be effectively avoided, and break away of the chip components from a substrate can be avoided. The semiconductor device comprises: one or more semiconductor chips each of which is flip chip bonded at a first surface thereof to the substrate; at least one chip components mounted on the substrate and in the proximity of the semiconductor chips; insulating underfill resin which covers the chip components and which fills at least part of a portion between the first surface of each of the semiconductor chips and the substrate; and a lid member which is bonded to a second surface of each of the semiconductor devices opposite to the first surface, via conductive adhesive resin.

Abstract: A semiconductor device assembly according to the present invention may comprise a semiconductor die having at least one contact pad thereon and a package substrate having at least one lead pad thereon. The package substrate is sized to receive the semiconductor die so that the contact pad on the semiconductor die is substantially aligned with the lead pad on the package substrate when the semiconductor die is positioned on the package substrate. A coil spring is positioned between the contact pad on the semiconductor die and the lead pad on the package substrate so that the axis of the coil spring is substantially parallel to the contact pad contained on the semiconductor die and the lead pad contained on the package substrate.

Abstract: A monolithically integrated semiconductor circuit apparatus includes circuit elements disposed on a semiconductor substrate. The circuit elements include at least one semiconductor memory device, drive circuits, and a digital logic component monolithically integrated on the semiconductor substrate. A first contact-making plane is provided which is closer to a main surface of the semiconductor substrate than a penultimate contact-making plane, which is closer to the main surface of the semiconductor substrate than a last contact-making plane. The first, penultimate, and last interconnect patterns electrically interconnect the plurality of circuit elements. A protection device is formed at least in a partial region of the penultimate interconnect pattern. The protection device includes at least a fuse or an antifuse and is assigned to a redundancy activation for defective memory cells and memory cell groups in the semiconductor memory device.