Patents Examined by Jigar P Patel
  • Patent number: 11971778
    Abstract: A continuous anomaly detection service receives data stream and performs continuous anomaly detection on the incoming data streams. This continuous anomaly detection is performed based on anomaly detection definitions, which define a signal used for anomaly detection and an anomaly detection configuration. These anomaly detection definitions can be modified, such that continuous anomaly detection continues to be performed for the data stream and the signal, based on the new anomaly detection definition.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: April 30, 2024
    Assignee: Splunk Inc.
    Inventors: Jacob Barton Leverich, Shang Cai, Hongyang Zhang, Mihai Ganea, Alex Cruise
  • Patent number: 11971777
    Abstract: A method in an illustrative embodiment of the present disclosure includes determining, utilizing a first diagnosis model deployed in a storage system, whether a cause of a fault belongs to environmental factors. The method further includes determining, responsive to determining that the cause of the fault belongs to the environmental factors, whether the fault can be solved locally in the storage system. The method further includes sending, responsive to determining that the fault cannot be solved locally in the storage system, the fault to a second diagnosis model, wherein the first diagnosis model is obtained by distilling the second diagnosis model. According to the method for fault diagnosis of the present disclosure, particular faults can be diagnosed and solved locally in a storage system, so that the workload of a customer support team of the storage system in a cloud can be reduced.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 30, 2024
    Assignee: Dell Products L.P.
    Inventors: Jiacheng Ni, Jinpeng Liu, Zijia Wang, Zhen Jia
  • Patent number: 11971789
    Abstract: A method of operating a storage device may include establishing a connection between a host and the storage device, detecting a crash of the storage device, suspending, based on detecting the crash, processing commands from the host through the connection, recovering from the crash of the storage device, and resuming, based on recovering from the crash, processing commands from the host through the connection. The method may further include notifying the host of the crash based on detecting the crash of the storage device. Notifying the host may include sending an asynchronous event notification to the host through the connection. Notifying the host may include asserting a controller status indicator. The method may further include receiving a reset from the host, and resetting a storage interface based on receiving the reset from the host. The method may further include maintaining the connection through a communication interlace.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Melky Arputharaja Siluvainathan
  • Patent number: 11966636
    Abstract: Certain aspects of the present disclosure provide techniques for committing log data in an application to a log data repository. An example method generally includes receiving, from an application, data to be committed to a remote storage location. A type of the received data is determined. The type of the received data is generally associated with a prioritization level and a compression mechanism to be used in committing the data to the remote storage location. An application execution context associated with the received data is determined. At a dispatch time associated with the prioritization level of the received data and the application execution context associated with the received data, a compressed data payload is generated and transmitted to the remote storage location. Generally, to compress the data payload, at least the received data is generally compressed based on the determined compression mechanism.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 23, 2024
    Assignee: INTUIT INC.
    Inventors: Waseem Akram Syed, Jian Fang, Venkata Suresh Babu Chilluri, Michelle Gu, Nikita Prakash Patil, Muralidhar Kattimani
  • Patent number: 11960974
    Abstract: An apparatus and method are provided for storing and processing quantum information. More particularly, a physical layout is provided to perform Floquet codes. The physical layout includes a quantum processor having an array of qubits (e.g., columns of tetrons or hexons in which Majorana zero modes are located on topological superconductor segments) with a gateable semiconductor devices forming interference loops to perform two-qubit Pauli measurements. Coherent links between qubits in a column enable certain two-qubit Pauli measurements, especially those additional two-qubit Pauli measurements used at a boundary surrounding a region of the bulk code. The two-qubit Pauli measurements are selected to minimize a size of the interference loops. Certain embodiments perform Floquet codes in six time steps. Hexagon embodiments tile the array of qubits with unit cells of 6-gon vertical (or horizontal) bricks. Square-octagon embodiments tile the array of qubits with unit cells of two 4-gon and two 8-gon bricks.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Roman Bela Bauer, Jeongwan Haah, Christina Paulsen Knapp
  • Patent number: 11960367
    Abstract: A Peripheral Component Interconnect Express (PCIe) device includes a plurality of lanes comprising a plurality of ports, a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the remaining of lanes, except for a fail lane from among the plurality of lanes, and an EQ controller performing an equalization operation for determining a transmitter or receiver setting of each of the remaining lanes, wherein the EQ controller determining a final EQ coefficient using a log information and an error information.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: April 16, 2024
    Assignee: SK HYNIX INC.
    Inventors: Yong Tae Jeon, Dae Sik Park
  • Patent number: 11948045
    Abstract: Methods, systems, and apparatus for parallel optimization of continuously running quantum error correction by closed-loop feedback. In one aspect, a method includes continuously and effectively optimizing qubit performance in-situ whilst an error correction operation on the quantum system is running. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gates associated with the quantum system. In some implementations, the physical qubits are spatially partitioned into one or more independent hardware patterns, where the errors attributable to each hardware pattern are non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved such that all physical qubits and operations are optimized. The method allows for the optimization of each section of a hardware pattern to be performed individually and in parallel, and can result is O(1) scaling.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 2, 2024
    Assignee: Google LLC
    Inventor: Julian Shaw Kelly
  • Patent number: 11940888
    Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: March 26, 2024
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Marcio Juliato, Manoj R. Sastry
  • Patent number: 11928016
    Abstract: Embodiments of the invention are directed to systems, method, and devices for detecting failures in distributed systems. A failure detection platform may identify anomalies in time series data, the time series data corresponding to historical network messages. The anomalies can be labeled and used to train a first predictive model. At least one other model may be trained using the time series data, the anomaly labels and a supervised machine-learning algorithm. A third model can be trained to identify a system failure based at least in part on the outputs provided by the first and the second model. The third model, once trained, can be utilized to predict a future system failure.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 12, 2024
    Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
    Inventor: Minghua Xu
  • Patent number: 11928015
    Abstract: A fault insertion device (FID) comprises a transceiver and an FPGA. The transceiver receives signals from a MIL-STD-1553/1760 communications bus. The FPGA evaluates the signals received from the communications bus against a set of rules stored by the FPGA. Based upon the set of rules, the FPGA can selectively modify messages received from the communications bus prior to transmission to a remote terminal or a bus controller that is configured to communicate on the communications bus.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 12, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jason P. Krein, Jeremy W. Giron, Matthew S. Geuss, Robert Nevett, IV, Stephen T. Simpson, Roger Martin Kilgore, Jacob Edward Leemaster
  • Patent number: 11914490
    Abstract: A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Jianmin Huang, Xiangang Luo, Ashutosh Malshe
  • Patent number: 11907047
    Abstract: A data storage device, and an error tolerance selecting method thereof which includes: writing data to data blocks of the data storage device; reading written data of the data blocks as read data; comparing the read data and the written data of each data column in the data blocks, and calculating a number of error bits in each chunk including a plurality of data columns accordingly; calculating a difference value between the number of error bits in the chunk and a first threshold value to store the difference value in an error tolerance list; and selecting a largest difference value in the error tolerance list as an error tolerance.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 20, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Sheng-Yuan Huang
  • Patent number: 11907059
    Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11907057
    Abstract: Various embodiments of the teachings herein include a fault processing method comprising: receiving two historical faults similar to a target fault; searching keywords in a description of the target fault and each historical fault, wherein the keywords are classified into N grades, and for each system component in a grade, the grade comprises at least one keyword for describing the component, wherein N is an integer no less than 2; for each of the N grades, counting a quantity of identical system components represented by the keywords in the text description of each historical fault and the target fault; and comparing a degree of similarity of each historical fault to the target fault according to the quantity of identical system components counted in each grade of the N different grades, wherein a historical fault relating to a larger number of high-grade identical system components has a higher degree of similarity to the target fault.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 20, 2024
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Xiao Yin Che, Hao Tian Hui, Jiao Jian Wang, Ruo Gu Sheng, Daniel Schneegaß
  • Patent number: 11899548
    Abstract: A method includes determining, by an analysis system, a system aspect of a system for an issue recovery improvement evaluation. The method further includes determining, by the analysis system, at least one evaluation perspective and at least one evaluation viewpoint for use in performing the issue recovery improvement evaluation on the system aspect. The method further includes obtaining, by the analysis system, issue recovery improvement data regarding the system aspect in accordance with the at least one evaluation perspective and the at least one evaluation viewpoint. The method further includes calculating, by the analysis system, an issue recovery improvement rating as a measure of system issue recovery improvement maturity for the system aspect based on the issue recovery improvement data, the at least one evaluation perspective, the at least one evaluation viewpoint, and at least one evaluation rating metric.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 13, 2024
    Assignee: UncommonX Inc.
    Inventors: Raymond Hicks, Ryan Michael Pisani, Thomas James McNeela
  • Patent number: 11876629
    Abstract: The present disclosure provides a method, a device, electronic equipment, and a storage medium for data transmission, wherein the method includes sending data acquisition commands to a plurality of target devices and turning on a timer; for any first target device of the plurality of target devices, detecting whether there is first target data transmitted by the first target device on the bus within a preset timing time; if yes, performing a data verification on the first target data and determining a communication flag bit of the first target device based on the check result; and determining whether to receive the first target data transmitted by the first target device based on the communication flag bit of the first target device.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: January 16, 2024
    Assignee: Hangzhou Keencool Intelligent Technology Co., Ltd.
    Inventors: Bin Shen, Xiang Zhang, Hangfei Tu
  • Patent number: 11874731
    Abstract: The system determines a first and a second snapshot of memory usage by processes in a computing system based on a predetermined time interval, wherein a respective snapshot indicates, for a respective process, memory usage corresponding to memory types including private memory and shared memory. The system computes, for processes common to the first and the second snapshots, a likelihood of memory leak for a process and memory type based on: an increase in an amount of heap memory and private memory; an increase in an amount of shared memory; and an increase in a total amount of private and shared memory. The system compares the computed likelihood for the process with a predetermined threshold. Responsive to determining that the computed likelihood for the process exceeds the predetermined threshold, the system performs a corrective action to address memory leak associated with the process.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: January 16, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregory B. Goslen, Christopher S. Murray
  • Patent number: 11841762
    Abstract: Provided are a data processing method and an apparatus thereof. The method includes: when data writing is to be performed for a target Trunk Group (TKG), determining whether the target TKG is available (S100); when the target TKG is available, performing data writing for the target TKG (S110); and, when the target TKG is unavailable, repairing the target TKG, and performing data writing for the repaired target TKG (S120).
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 12, 2023
    Assignee: Hangzhou Hikvision Digital Technology Co., Ltd.
    Inventors: Yang Xiang, Yuanzhi Qi, Jie Yan, Bin Zhang, Qi Wu, Ming Chen, Qingxiao Ni
  • Patent number: 11841773
    Abstract: An information handling system may include at least one processor, a physical storage resource, and a non-volatile memory other than the physical storage resource. The at least one processor may be configured to execute instructions for: storing learned profile data at the physical storage resource; in response to detection of a catastrophic event, copying the learned profile data from the physical storage resource to the non-volatile memory; and subsequent to a remediation event for the catastrophic event, restoring the learned profile data from the non-volatile memory.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: December 12, 2023
    Assignee: Dell Products L.P.
    Inventors: Jagadish Babu Jonnada, Nikhil Manohar Vichare, Ibrahim Sayyed
  • Patent number: 11836035
    Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Linnen, Aashish Sangoi, Kirubakaran Periyannan, Judah Gamliel Hahn