Abstract: Solar cells and other semiconductor devices are fabricated more efficiently and for less cost using an implanted doping fabrication system. A system for implanting a semiconductor substrate includes an ion source (such as a single-species delivery module), an accelerator to generate from the ion source an ion beam having an energy of no more than 150 kV, and a beam director to expose the substrate to the beam. In one embodiment, the ion source is single-species delivery module that includes a single-gas delivery element and a single-ion source. Alternatively, the ion source is a plasma source used to generate a plasma beam. The system is used to fabricate solar cells having lightly doped photo-receptive regions and more highly doped grid lines. This structure reduces the formation of “dead layers” and improves the contact resistance, thereby increasing the efficiency of a solar cell.

Abstract: Laser beams emitted by a plurality of laser sources are divided into a plurality of sub-beams, which are irradiated onto selected portions of an amorphous semiconductor on a substrate to crystallize the amorphous semiconductor. A difference in diverging angles between the laser beams is corrected by a beam expander. The apparatus includes a sub-beam selective irradiating system including a sub-beam dividing assembly and a sub-beam focussing assembly. Also, the apparatus includes laser sources, a focussing optical system, and a combining optical system. A stage for supporting a substrate includes a plurality of first stage members, a second stage member disposed above the first stage members, and a third stage member 38C, rotatably disposed above the second stage to support an amorphous semiconductor.

Abstract: This invention provides a method for fabricating a metal oxide semiconductor. A pad oxide layer, a mask layer and an insulator layer are formed in sequence on a substrate. The insulator layer and the mask layer are patterned to form an opening that exposes the pad oxide layer. A self-aligned ion implantation process is performed by using the insulator layer and the mask layer as a mask. The pad oxide layer exposed by the opening is removed. A gate is formed on the substrate exposed by the opening.

Abstract: Disclosed is a method to reduce step difference of a cell region and a peripheral region, and to increase the capacitance. A first intermetal insulating layer, a planarization layer and a second intermetal insulating layer are formed successively on the semiconductor layer including a storage node. A contact hole is formed by etching the first intermetal insulating layer, the planarization layer and the second intermetal insulating layer so that a selected portion of the storage node is exposed. A photoresist pattern in which a wave of saw-teeth shape is formed at sidewalls, is formed on the second intermetal insulating layer so as to fill the contact hole. Spacers are formed at both sidewalls of the photoresist pattern in which the wave of saw-teeth shape is formed. Herein, a wave of saw-teeth shape is formed at inner surfaces of the spacer owing to both sidewalls of the photoresist pattern. The photoresist pattern in which the waves of saw-teeth shape are formed at sidewalls thereof, is removed.