Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

Abstract: A method of manufacturing an electronic apparatus includes: providing a work substrate including a preliminary set module including an active area including a hole formation area; and a protective film covering at least one of an upper surface and a rear surface of the preliminary set module; radiating the laser beam to the work substrate from a first start point toward a moving path removing at least a portion of the work substrate to form a first start cutting line in the hole formation area, the moving path of the laser beam defined as a boundary between the hole formation area and the active area; radiating the laser beam along the moving path; and removing the hole formation area from the preliminary set module to form a module hole, wherein the first start cutting line forms a predetermined angle with respect to a tangential line of the moving path.

Abstract: A display apparatus including a substrate; a display area arranged on the substrate and including a plurality of pixels, and a peripheral area arranged outside the display area; a dam surrounding the display area; a crack detector arranged between the dam and an end of the substrate and electrically connected to at least one of the plurality of pixels; a crack prevention dam arranged between the dam and the end of the substrate; and an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer, each covering the display area and a portion of the peripheral area. The first inorganic layer and the second inorganic layer in the encapsulation layer extend to the end of the substrate.

Abstract: The application discloses a wiring structure, a display substrate and a display device. The wiring structure provided includes a plurality of hollowed pattern strings, each hollowed pattern string including a plurality of hollowed patterns arranged sequentially in a length extension direction of the wiring structure, each hollowed pattern including a hollowed region and a non-hollowed region. The non-hollowed region of any hollowed pattern in a hollowed pattern string at least partially overlaps the non-hollowed region of a hollowed pattern in a further hollowed pattern string adjacent to the hollowed pattern string, and the hollowed regions of the hollowed patterns in the plurality of hollowed pattern strings do not overlap each other. The wiring structure is particularly adapted for flexible display.

Abstract: A shadow mask used for OLED evaporation and a manufacturing method therefor, and an OLED panel manufacturing method. The shadow mask used for OLED evaporation includes: a semiconductor substrate including a front surface and a back surface opposite thereto, a recess penetrating the front surface and the back surface being provided in the semiconductor substrate; and a grid film layer provided on the front surface of the semiconductor substrate. A number of openings arranged in an array are provided in the grid film layer. Each of the openings has an upper portion and a lower portion. A width of the upper portion is greater than a width of the lower portion. The recess exposes the number of openings in the grid film layer and the grid film layer between adjacent openings.

Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.

Abstract: An array substrate and a display device are disclosed. The array substrate includes a base substrate. The base substrate includes a pixel area and a peripheral area surrounding the pixel area, wherein the pixel area and the peripheral area are provided with gate lines, and the peripheral area is provided with an electrostatic discharge branch, a first electrostatic protection unit, and an electrostatic protection line. The electrostatic discharge branch is connected in parallel to a preset section of the gate line, and the preset section of the gate line is located in the peripheral area. The first electrostatic protection unit is connected to the electrostatic discharge branch and the electrostatic protection.