Abstract: Systems and methods are provided for a secondary authentication of a memory module. A nonce key is written to a nonce register of a register array on the memory module, the nonce register being accessible over two different interfaces. In various embodiments, the nonce key may be generated by a management system of the computing platform after performing one or more authentication processes for a memory module over a management interface. Authentication information for use in performing authentication can be stored in an identification component on the memory module. If authentication is successful, the management system can generate the nonce key and write it to the nonce register. Upon receiving a request to access an address, a memory controller can read the nonce register of the memory module at the requested address and compare the nonce key to an identifier included in the request.

Abstract: A key value (KV) store, a method thereof, and a storage system are provided herein. The KV store may include a key logger; and a processor configured to receive a first command for storing a first KV in the KV store, write a first value of the first KV to a first NAND page, generate an extent map for identifying the first memory page including the first value, write the extent map to a second memory page, append an entry for storing the first KV to the key logger, and update a device hashmap of the KV store to include a first key of the first KV, upon a threshold being met within the key logger.

Abstract: Methods, systems, and devices for fast mode for a memory device are described. In some examples, a memory device may be initialized during a system boot procedure. The memory device may support multiple modes of operation, including at least a first mode that includes a first set of capabilities, and a second made that includes the first set of capabilities, as well as one or more additional capabilities. The memory device may perform the initialization while operating the memory device according to the first mode, which may include delaying one or more actions associated with the one or more additional capabilities. After the system boot procedure is complete, the memory device may operate according to the second mode, which may include performing an action delayed during the system boot.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

Abstract: A storage system is coupled to a cloud system that provides cloud volumes belonging to any of a plurality of tiers with different access performances. The cloud system changes a tier to which an externally-provided volume belongs based on a state of volume utilization in which the cloud volumes are utilized. A storage controller of the storage system provides a host computer with a volume created by allocating a page to an external volume that corresponds to the cloud volumes. In addition, the storage controller adjusts a state of volume utilization to control a tier to which the cloud volumes belong.

Abstract: Page request interface overhead reduction for virtual machine migration and write protection in memory may be provided by generating a page table associated with the memory; in response to receiving a write-protection command to prevent write-access to data from a portion of the memory, write-protecting a first range of memory addresses comprising the data write protected from the portion of the memory, wherein a second range of memory addresses comprises data not write protected in the memory; and modifying the page table to include a page table entry associated with the first range of memory addresses being write-protected, wherein write access to a memory address in the first range of memory addresses by a device during write-protection is tracked.

Abstract: A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.

Abstract: A resource allocation method and a storage device are provided. The storage device includes a disk enclosure and a plurality of controllers. Each controller includes a plurality of processors, each processor includes a plurality of processor cores, the plurality of controllers are separately coupled to the disk enclosure including a plurality of hard disks. The plurality of processors are configured to provide computing resources. The plurality of hard disks are configured to provide storage space. Logical addresses corresponding to the storage space are classified into several address segment sets, each address segment set includes one or more address segments, some of the computing resources are allocated to each address segment set, and are used to execute a data access request for accessing an address segment comprised in the address segment set. Computing resources used to process different address segment sets are from different processors or from different processor cores.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, store the received KV pair data in an intermediate storage location, match the received KV pair data to another one or more KV pair data stored in the intermediate storage location, where the matching is based on a utilization parameter of a storage container of the memory device, aggregate the matched received KV pair data and the another one or more KV pair data stored in the intermediate storage location, and program the aggregated KV pair data to the memory device.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, determine whether the KV pair data corresponds to a first tier or a second tier, where the second tier has a lower performance requirement than the first tier, and program the value of the KV pair data as padding data when the KV pair data corresponds to the second tier. The determining is based on a received hint of the KV pair data, a relative performance of the KV pair data, and a length of the KV pair data. The controller is configured reclassify the KV pair data based on a read frequency of the KV pair data.

Abstract: A low-latency file system file address space management method and system, and a medium. The method of the present invention comprises: generating a superblock and a block group allocation table from an address space of a storage device, wherein the superblock stores file system information and the allocation situation of block groups on a liner address space of the storage device, and the block group allocation table is used for marking the allocation situation of data blocks in the corresponding block group; when a file is created, dynamically creating or selecting a corresponding block group according to the size of a specified data block and allocating the data block; and writing file data into the allocated data block, and updating the block group allocation table and information of the superblock.

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

Abstract: A list of a available zones across respective SSD storage portions of a plurality of zoned storage devices of a storage system is maintained. Data is received from multiple sources, wherein the data is associated with processing a dataset, the dataset including multiple volumes and associated metadata. Shards of the data are determined such that each shard is capable of being written in parallel with the remaining shards. The shards are mapped to a subset of the available zones, respectively. The shards are written to the subset of the available zones in parallel.

Abstract: Methods, systems, and devices for memory device health evaluation at a host device are described. The health evaluation relates to a host device that is associated with a memory device that monitors and reports health information, such as one or more parameters associated with a status of the memory device. The memory device may transmit the health information to the host device, which may perform one or more operations and may transmit the health information to a device of another entity of a system (e.g., ecosystem) including the host device. The host device may include one or more circuits for transmitting and processing the health information, such as a system health engine, a safety engine, a communication component, or a combination thereof. Based on a determination by the host device or information received from an external device, the host device may transmit a command to the memory device.

Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including storing, on a volatile memory device, logical-to-physical (L2P) mapping data corresponding to sequentially written data, determining whether an L2P update criterion is satisfied, and in response to determining that the L2P update criterion is satisfied, updating an L2P mapping data structure based on the L2P mapping data. The L2P mapping data structure maintains an initial logical translation unit (LTU) of the sequentially written data, and a length of the sequentially written data from the initial LTU.

Abstract: Methods, systems, and computer program products for generating multi-dimensional host specific storage tiering are provided herein. A computer-implemented method includes maintaining information of a plurality of storage resources connected to at least one host device; configuring, based at least in part on the information, a plurality of partitions of the storage resources, each partition comprising multiple storage tiers, wherein the plurality of partitions is configured to provide physical migration paths between the multiple storage tiers within each of the partitions; detecting a change to the plurality of storage resources; and reconfiguring the plurality of partitions based at least in part on the detected change.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a hint calibration operation is needed, select a first hint mode out of a plurality of hint modes, generate one or more hints based on a selected hint mode, and select a hint mode based on one or more of a performance, quality of service, and power consumption of the data storage device. The controller is further configured to iterate through the plurality of hint modes during the hint calibration operation and operate based on the selected hint mode until the controller determines that another hint calibration operation is needed.

Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.

Abstract: The present invention is directed to realize a QoS function in the unit of a virtual volume group existing over a plurality of storage apparatuses. A management system of a storage system forms a virtual volume group by using a plurality of volumes provided by a plurality of storage apparatuses. In the virtual volume group, a QoS setting value including a data input/output amount is set. IO processing ability provided from each of the volumes to the virtual volume group is set so as to satisfy the QoS setting value. The management system sets the IC processing ability provided from each of the volumes to the virtual volume group on the basis of operation information of each of the volumes.