Abstract: Provided is a method of forming a thick metal silicide layer on a gate electrode. The method includes forming a gate electrode of a transistor on a semiconductor substrate, wherein a hard mask is formed on the gate electrode, forming a spacer on a sidewall of the gate electrode, forming a first silicide layer on a portion of the semiconductor substrate, adjacent to the spacer, forming an insulating layer on the first suicide layer to expose upper portions of the hard mask and the spacer, selectively etching the exposed upper portions of the hard mask and the spacer using the insulating layer as an etch mask until the top surface and the sidewall of the gate electrode are exposed, forming a metal layer on the exposed top surface and sidewall of the gate electrode, and forming a second silicide layer on the gate electrode by siliciding the metal layer.

Abstract: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.

Abstract: There are disclosed a stacked package formed by stacking semiconductor device packages and a manufacturing method thereof. Each package includes leads and connection terminals. A semiconductor chip is electrically connected to the connection terminals. A package body has the same thickness as that of the lead so as to expose the upper and the lower surfaces of the leads to the package body. Each of the packages is stacked on another package by electrically connecting the exposed upper and lower surfaces of the leads with each other. The manufacturing method has preparing lead frames, attaching an adhesive tape to the lower surface of the lead frame, bonding a semiconductor chip to the adhesive tape in the chip receiving cavity between the leads, connecting the semiconductor chip to the connection terminals, forming a package body, removing the adhesive tape; removing dam bars from the side frame, separating packages from the lead frame, and forming a stacked package by stacking a plurality of the packages.

Abstract: An ultrasonic-wave washing unit comprising an ultrasonic-wave vibrating plate to which an ultrasonic-wave vibrator is fixed by adhesive bonding, an ultrasonic-wave transmission plate opposed to the vibrating plate, a liquid supply means which supplies a liquid to a space defined between the vibrating plate and the transmission plate, and a liquid discharge means for discharging the liquid from the space.

Abstract: An apparatus and method for protecting die corners in a semiconductor integrated circuit. At least one irregular seal ring having two sides can be configured, wherein the irregular seal ring is located at a corner of a die utilized in fabricating a semiconductor integrated circuit. A dummy configuration for stress relief can then be arranged, wherein the dummy configuration is located at the two sides of the at least one irregular seal ring, thereby protecting the corner of the die against thermal stress and the semiconductor integrated circuit against moisture and metallic impurities. The irregular seal ring can be configured to generally comprise a non-rectangular seal ring. The irregular seal preferably comprises an octangular seal ring.

Abstract: A method of crystallizing amorphous silicon using a mask having a transmitting portion including a plurality of stripes, wherein end lines of at least two stripes are not collinear; and a blocking portion enclosing the plurality of stripes includes the steps of setting the mask over a substrate having an amorphous silicon layer, applying a first laser beam to a first area of the amorphous silicon layer through the mask, thereby forming a first crystallization region, moving the substrate in a first direction, thereby disposing the blocking portion of the mask over the first crystallization region, and applying a second laser beam to the first area of the amorphous silicon layer through the mask, thereby forming a second crystallization region.

Abstract: A method of testing an integrated circuit is provided, which includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate and a first channel is formed in the first dielectric layer in contact with the semiconductor device. A first contact pad mask layer is formed and a first contact pad in the first contact pad mask layer is formed in contact with the first channel. The first contact pad is used to test the first channel and the semiconductor device and the first contact pad mask layer and the first contact pad are removed.

Abstract: The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions is greater than the dopant concentration in the bulk substrate. The first doped region is substantially aligned with the gate electrode of the device, while the second and third doped regions are vertically spaced apart from the first doped region.

Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.

Abstract: A package that resists creation of particles in a package cavity. A package according to one embodiment of the present invention contains a mechanical device attached to the floor of the package substrate. Epoxy typically is used to attach the device. Electrical connections are provided by bond wires connecting bond pads on the substrate with bond pads on the device. A window is attached to the substrate to form a cavity around the device. A thin masking layer on portions of the package cavity surface prevents the surface from generating particles. The thin masking layer may be any material that resists particle generation. The masking layer on the cavity walls optionally extends out of the cavity and onto the upper surface of the package.

Abstract: In a trench isolation method, an etching mask pattern for forming a trench is formed on a semiconductor substrate. The substrate is etched to form a trench. An insulating layer is formed to fill the trench, and then a material layer is formed on the insulating layer. In this case, the material layer is made of material formed at a high temperature to density the insulating layer. The material layer and the insulating layer are planarly etched and the etching mask pattern is removed, so that a trench isolation layer is completed. Accordingly, although a densification process is avoided, it is possible to form a device isolation layer having a favorable surface profile.

Abstract: In a method of manufacturing a lead frame for use in a leadless package such as a quad flat non-leaded package (QFN), a base frame is first formed which includes a region for resin-molding a plurality of semiconductor elements to be mounted on one surface of the base frame, the region being partitioned into land shapes, and in which a die-pad portion and lead portions around the die-pad portion are defined severally for the individual semiconductor elements to be mounted in each of the partitioned regions for resin-molding. Next, an adhesive tape is attached to the other surface of the base frame, and subsequently a cut portion is provided at a portion corresponding to a region between two adjacent partitioned regions for resin-molding, of the adhesive tape.

Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.

Abstract: A method of forming a source/drain having a reduced junction capacitance and a transistor employing the same. In one embodiment, the method of forming the source/drain includes forming a recess in a substrate adjacent a gate of the transistor and forming a deep doped region below a bottom surface of the recess. The method also includes epitaxially growing a semiconductor material within the recess and forming a lightly doped drain region adjacent the gate.

Abstract: Chips C which have already been diced are attached to a ring frame F using an adhesive sheet, and a protective sheet S1 is attached to a circuit pattern surface of the chips C. The chips C, along with a ring frame F, are held in place on a table 27 of a protective sheet peeling apparatus 20. A supply portion for an adhesive tape T is disposed in the vicinity of a table 24, and the supplied adhesive tape T is attached to the protective sheet S1. When the protective sheet S1 is peeled from the circuit pattern surface, peeling starts from corner portions of the chips C or opposing corner positions by pulling the adhesive tape T.

Abstract: A die mold machine for molding a plurality of semiconductor assemblies on multiple substrate/leadframes includes a plurality of die mold layers stacked vertically one above the other to form a plurality of die mold sections. The top die mold layer has at least one aperture or die hall in the top most die layer and apertures or die halls in the in-between layers for passing molding compound which flows through the die hall in the top layer down through the die halls or apertures between the die mold layers into the die mold sections for molding semiconductor assemblies on said substrate/leadframes between said die mold layers.

Abstract: Methods for integrated circuit diagnosis, characterization or modification using a charged particle beam. In one implementation, the bulk silicon substrate of an integrated circuit is thinned to about 1 to 3 ?m from the deepest well, a voltage is applied to a circuit element that is beneath the outer surface of the thinned substrate. The applied voltage induces an electrical potential on the outer surface, which is detected as a surface feature on the outer surface by its interaction with the charged particle beam.

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.