Patents Examined by John Francis Wojton
  • Patent number: 11023327
    Abstract: A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 1, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Joseph Linnen, Ashish Ghai, Avinash Rajagiri, Srikar Peesari
  • Patent number: 11010083
    Abstract: Various techniques manage a storage system. Such techniques involve: in response to detecting that a first request of a plurality of requests initiated for a bulk request is completed, determining a response time length for the first request, the bulk request being used to migrate data from a first storage device to a second storage device, each request of the plurality of requests being used to read data from the first storage device and write data to the second storage device; determining an average response time length of the completed requests of the plurality of requests based at least in part on the response time length for the first request; and updating the number of the plurality of requests initiated for the bulk request based on the average response time length.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 18, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Changyu Feng, Jian Gao, Xinlei Xu, Lifeng Yang, Xiongcheng Li
  • Patent number: 10970216
    Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Kshitij A. Doshi, Francesc Guim Bernat, Daniel Rivas Barragan, Suraj Prabhakaran
  • Patent number: 10949354
    Abstract: In one embodiment, a safe data commit process manages the allocation of task control blocks (TCBs) as a function of the type of task control block (TCB) to be allocated for destaging and as a function of the identity of the RAID storage rank to which the data is being destaged. For example, the allocation of background TCBs is prioritized over the allocation of foreground TCBs for destage operations. In addition, the number of background TCBs allocated to any one RAID storage rank is limited. Once the limit of background TCBs for a particular RAID storage rank is reached, the distributed safe data commit logic switches to allocating foreground TCBs. Further, the number of foreground TCBs allocated to any one RAID storage rank is also limited. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 10922014
    Abstract: Systems and methods are disclosed for die access order variation to a memory having a multiple-die architecture. In certain embodiments, an apparatus may comprise a controller configured to assign a unique die access order to each set of multiple sets of related commands, a die access order controlling an order in which a plurality of dies of a solid state memory are accessed to perform the related commands. A first stream may be assigned a first die access order, and a second stream may be assigned a second, different die access order, thereby distributing the timing of die access collisions between the streams.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: February 16, 2021
    Assignee: Seagate Technology LLC
    Inventor: Jonathan Henze
  • Patent number: 10908832
    Abstract: Disclosed in some examples are methods, systems, machine-readable mediums, and NAND devices which create logical partitions when requested to create a physical partition. The controller on the NAND mimics the creation of the physical partition to the host device that requested the physical partition. Thus, the host device sees the logical partition as a physical partition. Despite this, the NAND does not incur the memory storage expense of creating a separate partition, and additionally the NAND can borrow cells for overprovisioning from another partition. In these examples, a host device operating system believes that a physical partition has been created, but the NAND manages the memory as a contiguous pool of resources. Thus, a logical partition is created at the NAND memory controller level—as opposed to at the operating system level.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kulachet Tanpairoj, Sebastien Andre Jean, Jianmin Huang
  • Patent number: 10861502
    Abstract: A shack-sensor apparatus may include a sensor configured to detect a positional state of a hard-drive drawer. The shock-sensor apparatus may also include a mounting component coupled to the sensor and configured to mount the sensor in a location to monitor the positional state of the hard-drive drawer. In addition, the shock-sensor apparatus may include a computing module, electronically coupled to the sensor, that analyzes sensor data provided by the sensor to predict a shock event of the hard-drive drawer and send, in response to predicting the shock event, a signal to at least one hard drive in the hard-drive drawer to prevent damage to the hard drive. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: December 8, 2020
    Assignee: Facebook, Inc.
    Inventor: Jason David Adrian
  • Patent number: 10776277
    Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj