Abstract: In a memory cell of an EEPROM or flash-EEPROM memory, the source and the drain of a floating-gate transistor forming the non-volatile memorizing device are connected together. It is shown that the capacitive behavior of the cell is then differentiated at the time of the reading depending on whether it is in a programmed state or in an erased state. This difference in behavior is used to differentiate the logic states.

Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

Abstract: An insulated gate semiconductor device (10) is fabricated by providing at least one ballast resistor (40) having a sheet resistance of at least one square. The ballast resistor (40) is formed in the emitter region (17) between two adjacent portions of the base region (26) at the top surface of the semiconductor body in which the device (10) is fabricated. The ballast resistor (40) improves the latch resistance of the device (10) in overload conditions.

Abstract: A quantum effect device which operates in a mesoscopic region and eliminates the need for making monochromatic electron waves for the operation and moreover can operate in a high temperature region. The quantum effect device comprises a first waveguide for connecting a first region and a second region, wherein carriers are injected into the first region and emitted from the second region, a second waveguide being branched off from the center of the first waveguide and connected to a third region, and a control region being formed in the branch part of the first and second waveguides for controlling a potential barrier. When the potential barrier is low, the control region emits carriers on the first waveguide from the second region and when the potential barrier is high, the control region leads carriers into the second waveguide from the first waveguide by quantum-mechanical reflection for emitting the carriers from the third region.

Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.