Patents Examined by John H Hur
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Patent number: 9601209Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.Type: GrantFiled: May 19, 2015Date of Patent: March 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hyun Kim, Young-Sun Min, Sung-Whan Seo, Won-Tae Kim, Sang-Wan Nam
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Patent number: 9496045Abstract: Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.Type: GrantFiled: December 19, 2014Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Robert E. Kilker, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
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Patent number: 9449705Abstract: A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.Type: GrantFiled: February 6, 2014Date of Patent: September 20, 2016Assignee: Apple Inc.Inventors: Ofir Shalvi, Naftali Sommer, Dotan Sokolov, Yoav Kasorla
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Patent number: 9424930Abstract: Methods, storage controllers, and systems for non-volatile storage element programming are described. One method includes programming user data in pages associated with a set of wordlines of an erase block of a non-volatile, solid-state storage element. The method further includes selecting at least one of the wordlines of the set programmed with the user data and restricting further programming of user data in the pages associated with the selected wordline. In some embodiments, the selected wordline occurs subsequent to the pages associated with the other wordlines of the set in a page programming order for the erase block.Type: GrantFiled: September 15, 2011Date of Patent: August 23, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Robert Barry Wood, Jea Woong Hyun, Hairong Sun
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Patent number: 9425055Abstract: A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.Type: GrantFiled: May 28, 2014Date of Patent: August 23, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Ko-Min Chang, Craig T. Swift
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Patent number: 9343122Abstract: A circuit configuration includes a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as a function of the control signal, into a first register unit optionally at least a part of the first set of input data or of the second set of digital input data and to write into a second register unit optionally at least a part of the first set of input data or of the second set of input data.Type: GrantFiled: July 8, 2014Date of Patent: May 17, 2016Assignee: Robert Bosch GmbHInventors: Matthew Lewis, Paulius Duplys
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Patent number: 9251905Abstract: A semiconductor integrated circuit includes a reference voltage generation circuit configured to generate a reference voltage, and a voltage changing circuit configured to generate a second voltage from a first voltage based on a difference between the second voltage and the reference voltage and apply the second voltage to a load capacitance. The reference voltage generation circuit includes a variable current source and a capacitor which are connected in series and is configured to change the reference voltage linearly.Type: GrantFiled: August 30, 2013Date of Patent: February 2, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masafumi Uemura, Masaru Koyanagi, Masahiro Yoshihara
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Patent number: 9202529Abstract: A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element.Type: GrantFiled: November 22, 2013Date of Patent: December 1, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Kazuhiko Kajigaya
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Patent number: 8908419Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: March 18, 2013Date of Patent: December 9, 2014Assignee: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 8897066Abstract: A method of programming a nonvolatile memory device includes sequentially programming first to (n?1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n?1)th logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n?1)th latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n?1)th logical pages, and latching new program data, received along with the second program command, in an nth latch of the corresponding page buffer and programming the data, stored in the first to nth latches of the page buffer, into a first physical page of a second memory block of the memory blocks.Type: GrantFiled: December 29, 2011Date of Patent: November 25, 2014Assignee: Hynix Semiconductor Inc.Inventor: Min Joong Jung
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Patent number: 8811063Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.Type: GrantFiled: July 31, 2013Date of Patent: August 19, 2014Assignee: Micron Technology, Inc.Inventors: Roy E. Meade, Bhaskar Srinivasan, Gurtej S. Sandhu
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Patent number: 8681549Abstract: A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.Type: GrantFiled: August 3, 2012Date of Patent: March 25, 2014Assignee: Apple Inc.Inventors: Ofir Shalvi, Naftali Sommer, Dotan Sokolov, Yoav Kasoria
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Patent number: 8462564Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.Type: GrantFiled: April 20, 2011Date of Patent: June 11, 2013Assignee: Spansion LLCInventors: Yonggang Wu, Guowei Wang, Nian Yang, Sachit Chandra, Aaron Lee
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Patent number: 8456935Abstract: In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.Type: GrantFiled: November 16, 2011Date of Patent: June 4, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Bradford L. Hunter, Shayan Zhang
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Patent number: 8325522Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: January 24, 2011Date of Patent: December 4, 2012Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
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Patent number: 7580318Abstract: An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in ‘no operation’ state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.Type: GrantFiled: September 21, 2005Date of Patent: August 25, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hoon Kim, Joung-Yeal Kim
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Patent number: 7315472Abstract: A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.Type: GrantFiled: May 25, 2006Date of Patent: January 1, 2008Assignee: Hynix Semiconductor Inc.Inventor: Hee Youl Lee
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Patent number: 7206215Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film. Embodiments include a method of operating an antifuse, comprising applying a voltage across electrodes of a capacitor having a tantalum oxynitride film and forming a hole in the tantalum oxynitride film.Type: GrantFiled: August 29, 2002Date of Patent: April 17, 2007Assignee: Micron Technology, Inc.Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
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Patent number: 7203086Abstract: In a data reading method, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell, reference signal generating data corresponding to a high level side is written to the memory cell, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data, and a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is written to the memory cell without using a bit line.Type: GrantFiled: March 23, 2006Date of Patent: April 10, 2007Assignee: Sony CorporationInventors: Toshiyuki Nishihara, Yukihisa Tsuneda