Abstract: A parity checking method and apparatus for a qubit, a superconducting quantum chip, an electronic device, and a storage medium are provided. The method includes: configuring a measurement system for a qubit excited state measurement environment, the measurement system including: a first data qubit, a second data qubit, and an auxiliary qubit; determining a first operational frequency parameter of the first data qubit; determining a second operational frequency parameter of the second data qubit; determining a third operational frequency parameter of the auxiliary qubit; determining a logic gate matching the qubit excited state measurement environment based on the first operational frequency parameter, the second operational frequency parameter, and the third operational frequency parameter; and checking parity of a qubit in the qubit excited state measurement environment according to the logic gate.

Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

Abstract: There is described a method for communicating data, the method comprising: receiving an incomplete data stream, wherein the incomplete data stream comprises a plurality of sequences of data points having respective values and a plurality of sequences of missing data points; receiving a missing data model; determining values for each of the plurality of sequences of missing data points, comprising: selecting a sequence of missing data points that has not previously been processed, wherein the sequence of missing data points to be processed is selected as a smallest sequence of missing data points of the plurality of sequences of missing data points that have not previously been processed; processing the incomplete data stream to determine values for the selected sequence of missing data points based upon the missing data model; updating the incomplete data stream to include the determined values for the selected sequence of missing data points; and wherein values for subsequent sequences of missing data points

Abstract: Embodiments are provided for error mitigation in quantum programs. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a compilation component that causes encoding of one or more qubits according to a circular repetition code at a time after operations on the one or more qubits and before readout.

Abstract: A device (150) is arranged on a source side of a wireless link (50) and receives data traffic from one or more source devices (201, 202, 203). The device (150) forwards the data traffic via the wireless link (50) and via a further device (11), which is arranged on a destination side of the wireless link (50), towards one or more destination devices (21, 22, 23, 24). The device (150) receives redundancy information from the further device (11). The redundancy information indicates redundant payload which is common to multiple data frames in the data traffic forwarded by the device (150). Based on the redundancy information, the device (150) removes the indicated redundant payload from at least a part of the data traffic to be forwarded by the device (150).

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.

Abstract: A testing circuit includes: a first sampling module configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; and a second sampling module configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal. The second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal.

Abstract: Devices, systems and methods for monitoring interconnect lines may include operations for transmitting, by a transmit block to a receive block, a first signal over a first interconnect line; executing, by the transmit block, a first transmit logic operation on the first signal with respect to a second signal, on at least one second interconnect line to generate a transmit signal; receiving, by the transmit block, a receive signal resulting from a receive logic operation executed by the receive block on a received first signal on the first interconnect line with respect to a received second signal received on at least one second interconnect line; executing, by the transmit block, a second transmit logic operation on the transmit signal with respect to the receive signal; and generating, by the transmit block and based on the executing of the second transmit logic operation, a result signal.

Abstract: A method of receipt status reporting in a communication device, comprising configuring (S1) said communication device for periodic receipt status reporting by associating a first status report type with a value of a first reporting periodicity parameter and associating a second status report type with a value of second reporting periodicity parameter, said first status report type being different from said second status report type and said first reporting periodicity parameter being different from said second reporting periodicity parameter, and periodically (S2) sending receipt status reports of said first type according to said associated value of said first reporting periodicity parameter and receipt status reports of said second type according to said associated value of said second reporting periodicity parameter.

Abstract: Test stimulus signals applied to at least one circuit under test are produced in a set of test stimulus generators as a function of test stimulus information loaded in test stimulus registers. Loading of the test stimulus information in the test stimulus registers is controlled as a function of test programming information loaded via a programming interface in a respective control register in a set of control registers. The test stimulus generators are activated as a function of the test programming information loaded in said control registers. Test outcome signals received from the at least one circuit under test are used to produce signature comparison signals, which are compared with respective programmable signature reference signals stored in a set of input signature registers, are produced in response to the signature comparison signals produced from the test outcome signals failing to match with the respective reference signals.

Abstract: A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.

Abstract: Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.

Abstract: A method and a memory device are provided. Data is obtained for a scan operation at an input buffer of a scan kernel in the memory device. The input buffer is adaptable to a first mode and a second mode of the scan kernel. Preprocessing of the data from the input buffer is performed to generate preprocessed data. A different type of preprocessing is performed for the first mode and the second mode. The preprocessed data is filtered to generate a filtered result. The filtered result is provided from the scan kernel to a controller of the memory device.

Abstract: Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.

Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

Abstract: A communication device transmits to a communication partner device or receives from the partner device a radio frame conforming to an IEEE 802.11 standard series, wherein a capability of HARQ (Hybrid Automatic Repeat reQuest) that a device that transmitted the radio frame has is indicated in a MAC (media access control) frame of the radio frame.

Abstract: Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.

Abstract: Implementing a camouflage of current traces generated by a hardware component having one or more set of digital elements defining a plurality of operational datapaths comprises adjusting (761) one or more working condition(s) of the hardware component, measuring (762) a reaction of the hardware component to the working condition(s) by a logic test circuit through processing data operations along a reference datapath having a minimum duration corresponding to at least the longest of the operational datapaths, and in response to detecting an error (763) along the reference datapath, modifying (764) the working condition(s) so that the error generated by the logic test circuit is cancelled. Applications to countermeasures to side-channel attacks.

Abstract: A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

Abstract: A basic logic element includes: a calculation unit configured to perform calculation processing; a self-diagnosis unit configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit and output a result of the determination as an authority signal; and an output control unit configured to control whether or not to output the result of the calculation performed by the calculation unit based on whether or not the authority to output data is retained by the management unit.