Abstract: A central processor for digital signal processing operates at a high clock rate. In the central processor, data is transferred and processed largely in parallel and simultaneously. A buffer is inserted in the data link between a data memory and an ALU by means of at least three data buses so that within one clock period, all necessary data transfers for a two-address operation of the ALU are performed by using the buffer. In particular, a unidirectional data bus and a bidirectional data bus transfer data from the buffer to the ALU, and the bidirectional data bus transfers the result of an ALU operation back to the buffer. Simultaneously with the transfers between the buffer and the ALU, a data transfer is performed between the data memory and the buffer. The data transfers and the data processing are controlled by a control unit in which a fixed program is stored segment by segment. The use of pipelining in the control unit permits a high processing speed.

Abstract: A method and apparatus for indexing and labeling electronic disks comprised of providing an open or transparent window covering a segment of the jacket of the disk having an opening into which a removable indexing label with a full or partial listing of the files stored on said disk may be placed.

Abstract: In a card image data processing system wherein a plurality of card images are recognized as one box (2, 2'), the card images are defined by form data common to the box and card data written in fields is defined by field definition information which is of the form data, and the fields are designated for processing contents of the fields, i.e., card data; the card images, including the form data, is displayed in a first window (41, 42) of the display unit, fields of the displayed card images are designated and processing instructions for the card data prepared, and the processing instructions are displayed in an instruction window (43) of the display unit and registered in the instruction code buffer. Processing of the card data of the card images is executed based on the registered processing instructions.

Abstract: A device for generating the audio information of a set of characters in which some characters are intoned or pronounced with a different voice character. The device includes means for making a distinction between a capital letter and a small letter presented. For a capital letter character, a speech pattern is formed in which the pitch or the voice character is modified, while maintaining their identity, with respect to a speech pattern for a small letter of the same character. The device also includes means for determining the position of a letter, preferably the last letter, of a word composed of characters presented and for forming a speech pattern for the relevant letter in which the pitch or the voice character is modified while the identity is maintained.

Abstract: One or more defective elements regularly occur in series-parallel-series digital units comprising several elements. The described system offers a solution for the construction of a series-parallel-series digital system by means of a number of series-parallel-series digital units comprising one or more defective elements; in this system only a part of the data stream passing through the system appears as being unreliable on the output thereof. Moreover, said unreliable part will always be situated within the same serial data stream, while the other serial data stream on the output will not be affected thereby.

Abstract: Disclosed is a memory system for reading and writing variable length data fields. Each of the data fields are addressed by the combination of a word address, a bit address, and a field length. Internal to the memory system, a total of 2N cells are addressed by each word address where N is the maximum field length. But only a portion of the addressed cells are selectively enabled in response to the bit address and field length. An N bit shifter right justifies the output data from the selectively enabled cells, and also realigns right justified input data to be written into the selectively enabled cells.

Abstract: An interrupt signal generating means comprising a digital-to-analog (D/A) converter and means for supplying to said D/A converter a series of binary numbers at least some of which point to service subroutines in a data processor, and when converted to dc voltages by the D/A converter have values which are equal to dc voltages originating in various peripheral devices which indicate a need for servicing by certain ones of the processor subroutines. A plurality of voltage comparators compare the dc output of the D/A converter with the condition indicating voltages generated by the peripheral devices and when equality of dc voltages occurs on the inputs of a given voltage comparator, an interrupt signal is generated and supplied to the processor which then accesses the subroutine pointed to by the corresponding binary number.

Abstract: A sensing apparatus for detecting impedance changes in a variable impedance matrix keyboard. A microcomputer is utilized to control the basic key intersection scanning and for accurately calibrating and adjusting the sensing threshold of the sense amplifier prior to testing each key intersection so that the effects of stray impedance and varying voltage levels may be compensated for. The micro computer supplies sense amplifier sensitivity threshold selection address codes to set the sensing level for the amplifier. Trial drive pulses are applied to a reference capacitor and are gated to the sense amplifier while the sensing level thereof is varied until no output is obtained. This effectively adjusts the sensing circuits for variable voltage power fluctuations occurring over a short time and compensates for variable capacitive effects not associated with actual key switch movements.