Abstract: The specification describes an analytical technique for determining trace levels of copper in a background matrix of titanium by dissolving the titanium and the copper impurity in HF, then selectively depositing the copper on a clean silicon surface. The silicon surface is then analyzed for the trace level of copper.

Abstract: A semiconductor device manufacturing process diagnosis system including a visual inspection device for detecting a physically abnormal part of a semiconductor device to be diagnosed, an LSI tester for measuring electrical characteristics of a semiconductor device and a diagnosis device and characterized in that the diagnosis device extracts, from among circuit blocks constituting a semiconductor device, a block contained in a predetermined region covering a physically abnormal part, determines whether an extracted block and an abnormal block causing abnormality of electrical characteristics are the same, with respect to a block discriminated as an abnormal block, detects a position causing abnormality of electrical characteristics within the block, and depending on whether a detected position substantially coincides with a physically abnormal part, determines whether abnormality of electrical characteristics derives from physical abnormality.

Abstract: A cleaner of this invention is a cleaner for inspecting projections and removes any substance, e.g., aluminum oxide, which attaches to needle points of probe needles, when the probe needles pierce into the cleaner. The cleaner has a cleaner layer and a substrate. The cleaner layer is constituted by an elastic material layer, and a filler having a surface state improving function of the inspecting projections and dispersed in the elastic material layer. As the filler having a surface state improving function, a powder including at least one of ceramic materials, e.g., sand, glass, alumina, Carborundum (trade name), and the like, or a fiber layer made of an inorganic fiber or organic fiber can be employed.

Abstract: The present invention is a method and apparatus for depositing a film on a substrate. According to the present invention a characteristic of a substrate is determined. The substrate is then heated by heat from an upper heat source and heat from a lower heat source wherein the ratio of heat supplied from the upper heat source relative to the lower heat source is dependent upon the determined wafer characteristic.

Abstract: Methods for testing a [A] tape carrier package (TCP) for an integrated circuit device that includes two sets of test pads. A first set of test pads are located along the outer edges of the TCP and are used to test the performance of the integrated circuit device once the TCP has been fabricated and assembled. A second set of test pads is also provided between the TCP outer leads and integrated circuit device for testing the performance of the device once the TCP has been removed from a printed circuit board.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A method of facilitating wafer level burn-in testing. The method may utilize a rerouting process to connect input and output connections of each chip on the wafer to a bus network. The bus network may be used to conduct wafer level burn-in testing and does not change the AC/DC operating characteristics of the chips.

Abstract: A method is provided for treating wafers on a low mass support. The method includes mounting a temperature sensor in proximity to the wafer, which is supported on the low mass support, such that the sensor is only loosely thermally coupled to the wafer. A temperature controller is programmed to critically tune the wafer temperature in a temperature ramp, though the controller directly controls the sensor temperature. A wafer treatment, such as epitaxial silicon deposition, is started before the sensor temperature has stabilized. Accordingly, significant time is saved for the treatment process, and wafer throughput improved.

Abstract: A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one embodiment, the circuit (110) comprises a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) provides a measurement of the voltage at the node (114) as an output to a pin (116). A reset circuit (122) is coupled to the pass circuit (118) and is operable to activate and reset the pass circuit (118). Finally, a pass control circuit (120) is coupled to provide an output signal to the pass circuit (118) that drives the pass circuit (118) when active to pass the voltage at the node (114) to the pin (116).

Abstract: A method for making an asymmetric MOS device having a notched gate oxide wherein a region of the gate oxide adjacent to either the source or drain is thinner than the remainder of the gate oxide. The resulting MOS device includes a channel under the notched region of the gate oxide with a relatively high concentration of mobile charge carriers.

Abstract: A method for producing a composite structure for microelectronic devices includes producing several microelectronic devices by means of a deposition method, pre-seeding a surface with growth seeds for a diamond and depositing the diamond layer from a gas phase. The diamond layer is provided with thin spots between the devices. According to the invention, the devices are laid down initially on a growth substrate directly and/or with the use of the material of the growth substrate. Following the deposition of the devices, the latter are seeded on their free surfaces for the diamond layer. The diamond layer is located on the seeded free surfaces of the devices.

Abstract: A method to form a shallow trench isolation (STI) structure includes forming a trench on a semiconductor substrate. Then a channel stop is formed under the trench. A pad oxide layer and a silicon nitride layer are sequentially formed over the substrate. A side-wall spacer is formed over the silicon nitride layer on each side of the trench. An oxidation process is performed to oxidize the side-wall spacer. Another side-wall spacer and oxidation are repeatedly performed until the trench is filled with oxide. An oxide layer is formed over the substrate. Then an active ion etching process is performed to remove the layers above the substrate other than the trench region. The STI structure then is formed.

Abstract: Disclosed is a substrate used in performing a burn-in test of the integrated circuit chip prior to packaging the chip and a method for manufacturing a known good die using the same. The substrate includes a body having a plurality of through holes; a plurality of metal lines formed on one surface of the body and electrically connected to a plurality of bonding pads of the integrated circuit chip; and a plurality of pins each inserted into the respective corresponding holes and electrically connected to the respective corresponding metal lines and also projected from a surface opposite to the surface on which the metal lines of the substrate are formed. Moreover, the method of manufacturing a known good die includes performing a burn-in test in a state in which the integrated circuit chip is adhered to the substrate such that the bonding pads of integrated circuit chip are electrically connected to the metal lines of the substrate.

Abstract: A categorization of a particular semiconductor wafer based on void size is obtained from sigma data and T0.1% failure data that has been obtained from wafers subjected to isothermal testing. The sigma data and the T0.1% failure data for the particular wafer is compared to stored data corresponding to ranges for sigma and T0.1% data for each of a plurality of void categories, and the particular wafer is categorized based on the stored data. The T0.1% failure data is computed based on a T50% failure data and the sigma value, so that small sample sizes can be utilized to obtain the stored data.

Abstract: A method of forming a CVD nitride (e.g., titanium nitride) film on a substrate. The as-deposited nitride film is treated by a plasma of a high power density (preferably between approximately 200 W and 300 W) for a prolonged duration of time (preferably between approximately 32 s and 52 s) to reduce the tendency of the resistance and thickness of the as-deposited film to change because of either time of exposure to atmosphere or subsequent processing steps.

Abstract: A method of forming self-aligned contact by using silicon spacers is provided.

Abstract: A method for controlling semiconductor processing equipment in real time, includes measuring a characteristic value of a product of a first process performed by a first piece of equipment. Then it is determined whether the characteristic value of the product is within a predetermined acceptable product range stored in a host computer. A second process is stopped from operating on the product when the product is not within the range. Otherwise, when the product is within range, the process is tested using a main test that includes computing a main statistic using the characteristic value of the product and determining whether the main statistic is within a predetermined control limit range. Then, if the main test is not passed, the process is interrupted, including stopping the first piece of equipment and postponing the second process from operating on the product.

Abstract: A semiconductor device having a reduced polysilicon gate electrode width is provided along with a process for manufacturing such a device. In accordance with the present invention, a semiconductor device may be formed by forming an oxidation-resistant barrier layer over a substrate. At least one polysilicon block is formed over the barrier layer. A dopant is implanted through the barrier layer into the substrate. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces and thereby reduce the width of the block. The oxide layer then can be removed to form a gate electrode having a reduced width. Plural implantations and oxidation-removal can be carried out as desired.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate insulating film on a substrate, forming semiconductor layer on the gate insulating film, selectively removing the semiconductor layer to form first and second gate electrodes, implanting ions of a first conductive type into the first gate electrode, and implanting impurity ions of a second conductive type into the second gate electrode.

Abstract: A process for fabricating a two-transistor EEPROM cell that includes a self-aligned stack gate etch step. In the self-aligned stack gate etch step, poly 2 word lines are used as a self-aligned mask to define edges of a poly 1 floating gate that are parallel to the edges of the poly 2 word line, and a patterned photoresist layer is used to define poly 1 access transistor lines. The process provides for employing a self-aligned stacked gate etch without risk of silicon substrate trenching. The process also provides for the fabrication of two-transistor EEPROM cell arrays of high packing density since the need for misalignment driven poly 2 overlap of poly 1 is eliminated.