Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: Described is a computer-implemented method for preventing time out during data transfer to an input/output device. Dummy data is generated and transferred to the input/output device at a time during data transfer, such as when a time out event may occur that would end the data transfer. The transfer of dummy data prevents a time out event from occurring.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: A model and access method for devices to be homogenous irrespective whether they be character or block types. The access method is closely coupled between a host processor and the input/output (I/O) ports either through the data ports to the FIFOs (First-In-First-Out), or the control ports of the devices. Data transfers to the devices are effected through their data ports, while the control words in the form of bytecodes are sent through the control ports. The access method enables parallel processing within independent devices as they can execute device specific codes in parallel with the system software or kernel. The bytecodes are portable across hardware platforms since they serve as command words for configuration of devices and command instructions for the burst mode transfer of data between devices and a processor.

Abstract: An I/O processing system includes an operating system configured to control an input/output (I/O) device, which executes an I/O operation in the I/O processing system. The I/O processing system further includes a channel subsystem module configured to output an interrogation command signal while the I/O device executes an I/O request. The I/O device returns an I/O status signal indicating a status of an ongoing I/O request, and the operating system is configured to dynamically determine a timeout event of the I/O request based on the status of the ongoing I/O request.

Abstract: A method, program and/or system reads first data through a first path from a location in a data storage. Second data is read through a second path from the same location in the data storage. The first data is compared to the second data. A match between the first data and the second data indicates that the first path did not encrypt the first data. A mismatch between the first data and the second data indicates that the first path encrypted the first data.

Abstract: Packet information is stored in split fashion such that a first part is stored in a first device and a second part is stored in a second device. A split packet transmission DMA engine receives an egress packet descriptor. The descriptor does not indicate where the second part is stored but contains information about the first part. Using this information, the DMA engine causes a part of the first part to be transferred from the first device to the DMA engine. Address information in the first part indicates where the second part is stored. The DMA engine uses the address information to cause the second part to be transferred from the second device to the DMA engine. When both the part of the first part and the second part are stored in the DMA engine, then the entire packet is transferred in ordered fashion to an egress device.

Abstract: The present disclosure relates to an electronic device and a data transmission system. A first electronic device includes a micro universal serial bus (USB) interface, a central processing unit (CPU) and a diode, wherein a pull-circuit for an identity (ID) pin of the CPU is coupled to a line between the ID pin of the CPU and an ID pin of the micro USB interface; the diode is coupled between the ID pin of the CPU and the ID pin of the micro USB interface, and is coupled between the pull-up circuit and the ID pin of the micro USB interface; the diode has a conducting direction from the ID pin of the CPU to the ID of the micro USB interface. With the present disclosure, the electronic device may be prevented from being damaged.

Abstract: A system and method are provided for generating interrupts in a computer system using limited interrupt virtualization hardware. A peripheral component interconnect express (PCIe) device atomically sets one or more bits in a posted interrupt vector (PIV) of a target central processing unit (CPU), and sends an interrupt to the target CPU, the interrupt notifying the target CPU of changes to the PIV. Atomically setting the one or more bits may include executing a compare-and-swap function, executing a fetch-and-add instruction to increment a DWORD corresponding to the one or more bits in the PIV by a value of 2 ^ (b mod 32), using PCIe byte enables to write to a single byte in the PCIe address space that contains the one or more bits, using a helper CPU, performing a PCIe swap to the PIV, or storing the PIV in a memory of the PCIe device.

Abstract: A method, system and computer program product are disclosed for routing data packet in a computing system comprising a multidimensional torus compute node network including a multitude of compute nodes, and an I/O node network including a plurality of I/O nodes. In one embodiment, the method comprises assigning to each of the data packets a destination address identifying one of the compute nodes; providing each of the data packets with a toio value; routing the data packets through the compute node network to the destination addresses of the data packets; and when each of the data packets reaches the destination address assigned to said each data packet, routing said each data packet to one of the I/O nodes if the toio value of said each data packet is a specified value. In one embodiment, each of the data packets is also provided with an ioreturn value used to route the data packets through the compute node network.

Abstract: A master device has a slave port and a redundant slave port for communicating with slaves according to a network protocol, e.g. EtherCAT, via data packets including a circulating bit. The slaves are arranged in a sequence starting at the slave port, and are connected via a communication medium. A respective slave in the sequence detects whether the connection to its processing receiver is lost, and, if so, internally transfers any data packets from its forwarding arrangement to its processing arrangement, while setting the circulating bit. The master device has a switcher unit coupled to the redundant slave port and a last slave in the sequence. The switcher unit transfers data packets from the switcher receiver to the switcher transmitter, and detects whether a circulating bit is set. If so, the unit switches off said transferring and switches on a connection between the redundant slave port and the switcher for transferring replicated packets to the sequence.

Abstract: Circuits and methods are disclosed that allow devices to control the flow of DMA transfers to or from the devices using a token based protocol. In one example implementation, a DMA circuit includes a transfer control circuit that performs data transfers over a first data channel of a device, when transactions on the first data channel are enabled. The DMA circuit includes a flow control circuit that increments a token count for a data channel of a device when a token for the data channel is received and decrements the token count for each data transfer on the data channel performed by the DMA circuit. The flow control circuit enables data transfers on the data channel when the token count is greater than 0, and otherwise, disables data transfers on the data channel.

Abstract: Provided are a method and a device for executing an application, in which a second external device is communication-connected while the device executes the application along with a first external device and the device executes the application along with the first device and the second external device based on characteristic information of the first external device and the second external device. Also, in the method of executing an application, one or more external devices are connected while a device executes the application and the device and the one or more external devices execute the application together.

Abstract: Methods, physical computer-readable media, and devices are provided that allow re-enumeration to be initiated on a USB 3.0-compatible device. The method includes establishing a connection with a host, transmitting an indicator from the device to the host to cause a Link Training and Status State Machine (LTSSM) of the host to move from active state (U0) to one of SS.Inactive and RX.Detect, synchronizing the device with the host, and presenting a new configuration of the device to the host.

Abstract: A method and system for storing data for retrieval by an application running on a computer system including providing a tiered caching system including at least one cache tier and a base tier, storing data in at least one of said at least one cache tier and said base tier based on a policy, and presenting an application view of said data to the application by a means to organize data. The invention optionally provides an additional overflow tier, and preferably includes multiple cache tiers.

Abstract: For simplified projection of a cascaded fieldbus system which includes a first fieldbus with a plurality of first bus devices, a second fieldbus subordinate to the first fieldbus with a plurality of second bus devices and a third fieldbus subordinate to the second fieldbus with a plurality of third bus devices, an example embodiment of the invention provides that the second fieldbus is connected to the first fieldbus via a fieldbus access node device, and therefore bus devices of the second fieldbus are presented as virtual modules of the first fieldbus, and that a connection device, via which the third fieldbus is connected to the second fieldbus, is presented as a virtual fieldbus access node module of the first fieldbus, and therefore the remaining bus devices of the third fieldbus are presented as virtual modules of the first fieldbus.

Abstract: In one embodiment, to determine what tasks may be offloaded to a peripheral hardware device (e.g., to be performed in hardware on the peripheral device, rather than on the CPU(s) of the host computer), an indication from the at least one peripheral hardware device may be provided, without the peripheral hardware device first being queried to determine the task offload capabilities provided by the peripheral hardware device. In one embodiment, a large packet that includes a plurality of extension headers may be offloaded to the peripheral hardware device for segmentation. An indication of the offset where the extension headers end may be provided in connection with the large packet. In another embodiment, a packet with extension headers that come before an encryption header in the packet are not offloaded to peripheral hardware device for encryption, while packets with no extension headers before the encryption header may be offloaded.

Abstract: A data processing apparatus includes a shared buffer; an issuing unit that issues a write address for writing incoming data to the shared buffer; a receiving unit that receives a returned read address for the data read from the shared buffer; a monitoring buffer that saves information indicating use status of an address for the shared buffer; and a monitoring unit that monitors write address issuance and returned read address reception, changes the information for the write address, from an unused state to a used state, when the write address is issued, and changes the information for a read address to be returned, from a used state to an unused state when the returned read address is received. The monitoring unit determines the address for the shared buffer is overlapping, when the information for the write address indicates a used state when the write address is issued.

Abstract: A data transmission architecture includes a local system and a peripheral system. A core computing unit and the peripheral hub of the local system integrate display data and transmission data and transmit integrated data to the image transmission unit. A driving circuit of a display panel of the image transmission unit is utilized to transform the integrated data into a first electrical signal. A data transmission between the local system and the peripheral system utilizes at least one electrode of the display panel to transmit the first electrical signal to retrieve the transmission data. A transmitting device of the peripheral system transmits a second electrical signal. A receiving device of image transmission unit retrieves the second electrical signal. Then the receiving device transmits the second electrical signal to the peripheral hub. Accordingly the data transmission architecture can be utilized in data/files transmission, and cooperating with existing transmission system.

Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.