Abstract: A system, like a video on demand server, retrieves blocks of data from a storage medium 100 and supplies the data to users in the form of at maximum nmax data streams. Upon creation, a data stream is in a new state in which no sufficient data is present for consumption by a user, whereas a user may consume data for a data stream in an active state. A scheduler 170 repeatedly selects a group of data streams for which a data block of a predetermined size needs to be read and causes a reader 180 to read the data in one sweep and to store the read data in buffers 125. The group is formed by active data streams whose associated buffers 125 have room for storing the data block. The scheduler 170 variably determines the size of the data block for each next sweeping operation through an expression that, with respect to a number of data streams, is substantially based on an actual number nact of active data streams instead of nmax.

Abstract: The device has a first optical system 11 and a second optical system 12 which emit and receive laser light of different wavelengths, and is provided with light combining and dividing device (interference filter) 13, which combines lights emitted from the semiconductor lasers 11A of the respective optical systems and divides lights reflected from a recording medium 16 (or 17), guiding then to corresponding photosensors. Between this interference filter 13 and the objective lens 15 is located a phase plate which serves to change the phase distribution of one or the other wavelength from the first or second semiconductor laser 11A. This allows the above-mentioned object to be attained.

Abstract: A microcomputer is capable of having a CPU calculate a suitable bit rate with respect to a host computer, and of setting accordingly an appropriate erasure time forestalling excess erasure of an internally furnished flash memory, regardless of the operating frequency of the microcomputer. The erasure time is set according to a number of clock signal cycles calculated by the CPU, based upon a measured number of cycles taken during a predetermined period of receiving serial data from the host computer.

Abstract: A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal.

Abstract: A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).

Abstract: A method and apparatus in a computer system selectively stores CPU state related information in parallel in a first and a second set of registers. The two sets of registers can selectively transfer data in parallel therebetween to restore the CPU state related information used by the CPU. The second set of registers cm be organized in a cascaded structure or in selective banks of registers to keep track of multiple CPU state related information such as during nested interrupts. The second set of registers can tansfer data with a third data storage device asynchronously to the operation of the CPU.

Abstract: An apparatus and method are provided for virtual memory mapping and transaction management in an object-oriented database system having permanent storage for storing data in at least one database, at least one cache memory for temporarily storing data, and a processing unit which runs application programs which request data using virtual addresses. The system performs data transfers in response to memory faults resulting from requested data not being available at specified virtual addressed and performs mapping of data in cache memory. The data in the database may include pointers containing persistent addresses, which pointers are relocated between persistent addresses and virtual addresses.

Abstract: A computing apparatus has a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size. An address bus of the computing apparatus is configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size. The address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N.

Abstract: In a data processing system comprising a host system and a memory device including a data storage medium of a predetermined size and corresponding capacity, a secure method of managing available capacity of the storage medium by: maintaining an authentication list comprising a plurality of entries including information uniquely identifying a plurality of memory devices; selecting a section of said data storage medium for data storage, said section having a size representing the available capacity of the memory device; and maintaining identification information in the memory device uniquely identifying the memory device.

Abstract: In evicting data from a first cache in a level other than the lowest in a multilevel cache hierarchy, data is written to the system bus and snooped back into a second cache on a lower level in the cache hierarchy. The need for a private data path between the two caches is thus eliminated, and the second cache memory need not be dual-ported. The reload path employed for updating the second cache is reused to snoop cast-outs off the system bus. As a result of the first cache evicting data via the system bus, the second cache never contains data which is modified (M) with respect to system memory and other devices in a multiprocessor system get updated earlier. The need for error correction code (ECC) checking is eliminated, together with the associated additional bits, and may be replaced by simple parity checking. The bus into the second cache thus requires fewer bits, consumes less area, and may be operated at a higher frequency.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: Data in a write cache is coalesced together prior to each destage operation. This results in higher performance by destaging a large quantity of data from the cache with each destage operation. A root item of data is located, and then a working set of data is collected by identifying additional data in the cache that will be destaged to locations in the storage device adjacent to the root item of data. The root item of data may be identified by starting at the location of the least recently accessed data in the cache, and then selecting a root item of data at a lower storage device address than the least recently accessed data, or may be chosen from a larger than average group of data items that were stored together into the cache. To speed execution, data items are added to a working set by, where possible, scanning an queue of data items kept in access order to locate data items at adjacent storage locations.

Abstract: To avoid multiplexing within the critical address paths, the same address field is employed as a index to the cache directory and cache memory regardless of the cache memory size. An increase in cache memory size is supported by increasing associativity within the cache directory and memory, for example by increasing congruence classes from two members to four members. For the smaller cache size, an additional address “index” bit is employed to select one of multiple groups of address tags/data items within a cache directory or cache memory row by comparison to a bit forced to a logic 1.

Abstract: A data processing system and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of caches and a plurality of processors grouped into at least first and second clusters, where each of the first and second clusters has at least one upper level cache and at least one lower level cache. According to the method, a first data item in the upper level cache of the first cluster is stored in association with an address tag indicating a particular address. A coherency indicator in the upper level cache of the first cluster is set to a first state that indicates that the address tag is valid and that the first data item is invalid. Similarly, in the upper level cache of the second cluster, a second data item is stored in association with an address tag indicating the particular address. In addition, a coherency indicator in the upper level cache of the second cluster is set to the first state.

Abstract: A method for implementing a graphics address remapping table as a virtual register in system memory. The remapping table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data. The method uses an indirect addressing scheme that enables the individual virtual registers of the remapping table to be accessed in response to a transaction request. Accessing a selected virtual register indirectly requested by the transaction request enables the method to access graphics data pointed to by the selected virtual register.

Abstract: A method and system in accordance with the present invention provides additional addressable space on a disk for use by a host processor using a virtual data storage subsystem. The method and system includes defining at least one of a plurality of extended image devices on a disk and requesting an instant image to be addressed to an extended image device utilizing channel command words by a host processor. The method and system also includes reading the instant image utilizing commands, such as channel command words or common descriptor blocks, by the host processor. In a method and system in accordance with the present invention, a plurality of extended image devices are defined as extensions of a primary functional device. Data may be transferred between at least one of the plurality of extended images and the primary functional device, or between at least one of the plurality of extended image devices and another of the plurality of extended image devices.

Abstract: Disclosed is a system for copying data sets from a first storage device to a second storage device. The first storage device is managed by a first controller and the second storage device is managed by a second controller. The first controller receives a command to copy a plurality of data sets from the first storage device to the second storage device. First and second data structures are generated to include fields corresponding to the data sets. The fields initially indicate that the data sets have not been copied. For the data sets subject to the copy command, the first controller transfers a copy of the data set to the second controller. The second controller stores the copy of the data set received from the first controller in the second storage device. The field in the first data structure corresponding to the data set copied to the second storage device is then modified to indicate that the data set was copied to the second storage device.

Abstract: A controller chip has programmable registers that control the operation of the controller chip. The controller chip connects to a microprocessor and bus controller through a bus that performs burst cycles. Although only one address (the starting address) is sent over the bus during the burst cycle, multiple data words are sent in the burst. These data words are written to addresses that follow the starting address in a fixed burst sequence. Programmable registers are accessed in an order that is not the fixed burst sequence. The programmable registers are accessed in a non-sequential order in a single burst cycle by using a mapping control word. The starting address is is set to the address of a mapping control register in the controller chip. The mapping control word is sent as the first data word after the starting address. The mapping control word is decoded to determine which of the programmable registers are to be written during the burst cycle.

Abstract: A method and apparatus for maintaining a predetermined minimum read rate from a disk drive system, the disk drive system including a read/write cache memory, effect control over the write rate in response to data provided from the disk drive system. A host computer requests write cache utility factor information from the disk drive system. The response to the request provides the host computer with necessary information about the cache memory to enable it to control the write rate to not jeopardize the continuing flow of read data, for example, data for an audio or video decoding application. The host computer periodically samples the utilization of the cache memory and employs one of several methods for controlling the write rate to avoid adversely affecting the read data rate.

Abstract: A method and apparatus for receiving status information from shared logical memory modules in a computer system including redundant memory. The status information includes whether the shared logical memory modules are in a transitional state and the number of logical memory modules in the mirror set. When shared logical memory modules are added or removed from redundant memory they go through a transitional state when the memory card may respond to a request for data held on the card, but that data may be unreliable. Checking this status information allows better error checking of data and fault detection of the shared logical memory module.