Abstract: A complementary thin film transistor drive back-plate and manufacturing method thereof, a display panel.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The semiconductor fin includes a well region, a first doped region, and a second doped region. The first doped region and the second doped region are respectively adjacent to and being separated by a first portion of the well region. The device also includes a first gate structure on the semiconductor fin between the first doped region and the second doped region, and a first conductive structure electrically connecting the gate structure and the first doped region to a same potential. The ESD protection device can also have a third doped region and a second gate structure coupled to the same potential. The device also has a second conductive structure for connecting to a point between an external signal and a circuit to be protected.

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

Abstract: Embodiments of the present application relate to the use of quantum dots mixed with spacer particles. An illumination device includes a first conductive layer, a second conductive layer, and an active layer disposed between the first conductive layer and the second conductive layer. The active layer includes a plurality of quantum dots that emit light when an electric field is generated between the first and second conductive layers. The quantum dots are interspersed with spacer particles that do not emit light when the electric field is generated between the first and second conductive layers.

Abstract: A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first connecting layer to a first metallic contact and the second side being connected by a second connecting layer to a second metallic contact, the first side having a diode element in a middle area and having a further diode element in an edge area of the first side, which has crystal defects as a result of a separating process of the plate-shaped semiconductor element, the first connecting layer only establishing an electrical contact to the diode element and not to the further diode element and, on the first side, the further diode element having an exposed contact, which may be electrically contacted by the first connecting layer.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin comprising a channel region for a fin field effect transistor (finFET). A gate oxide layer is then formed on the channel. The gate oxide layer is treated with a nitrogen containing agent so as to form a nitrogenous layer and an interfacial layer. The nitrogenous layer is then removed. A high-k dielectric layer is formed on the interfacial layer. A metal gate is formed on the high-k dielectric layer. The nitrogenous layer is removed by rinsing the semiconductor fin with deionized water. The gate oxide and interfacial layer contains the same material.

Abstract: A resin composition for semiconductor encapsulation, containing (A) an epoxy resin, (B) a phenolic resin-based curing agent, (C) an inorganic filler, and (D) amorphous carbon, wherein the amorphous carbon of the component (D) contains 30 atomic % or more of an SP3 structure and 55 atomic % or less of an SP2 structure.

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

Abstract: A method for producing at least one optoelectronic semiconductor component and an optoelectronic semiconductor component are disclosed. In an embodiment, the method includes providing a semiconductor layer sequence comprising a first semiconductor material configured to emit a first radiation and applying a conversion element at least partially on the semiconductor layer sequence via a cold method, wherein the conversion element comprises a second semiconductor material, and wherein the second semiconductor material is configured to convert the first radiation into a second radiation.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: A method for forming a phase change random access memory is provided. The method includes providing a substrate having a surface; and forming a dielectric layer on the surface of the substrate. The method also includes forming a through-hole penetrating through the dielectric layer; and forming an adhesion layer on inner surface of the through-hole. Further, the method includes forming a metal layer doped with inorganic ions on the adhesion layer to reduce over-etching of the metal layer and increase heating efficiency of the metal layer on the surface of the adhesion layer; and forming a phase change layer on the dielectric layer, the adhesion layer and the doped metal layer.

Abstract: A light emitting device includes a base structure and a light emitting element. The light emitting element includes a first electrode and a second electrode. The first electrode includes a first electrode surface. The second electrode is separately provided from the first electrode. The second electrode includes a second electrode surface. The second electrode surface is spaced apart from the first electrode surface in a second direction different from a first direction. The second electrode surface includes a first part and a second part. The first part extends in a third direction different from each of the first direction and the second direction. The second part extends from the first part in the second direction. At least part of the second part has a curved profile extending from the first part when viewed in the first direction.

Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.

Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.

Abstract: A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.

Abstract: Two-terminal memory devices can be formed in part within a dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of metal particles employed in integrated circuit fabrication. This dielectric material can be protected from other fabrication processes corrosive to the dielectric material (e.g., CMP, HF clean, etc) by a silicon containing liner. Use of the silicon containing liner can enable a minimum thickness of the dielectric material to be preserved and can facilitate step height differences between adjacent material surfaces that form a two-terminal memory device to be on the order of less than about five angstroms. This small step height difference, particularly when underlying a switching layer of the two-terminal memory device, can yield excellent switching characteristics.

Abstract: Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate and an isolation structure formed on the substrate. The first fin structure is embedded in the isolation structure, and the first fin structure has an upper portion and a lower portion. The upper portion is above the isolation structure, and the lower portion is below the isolation structure. The FinFET device structure also includes a protection layer formed on the sidewalls of the lower portion of the first fin structure.

Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.