Abstract: A method for performing a common cancel (CC) function on a dynamic random access memory (DRAM) semiconductor device to improve reliability and speed of a memory system. The CC function rakes advantage of the intrinsic delays associated wit memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero larencies for read and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuitt The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to the shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture.

Abstract: A sequential buffer for a magnetic tape data storage system comprises a plurality of segments. A buffer management system buffers data in the sequential buffer, conducting a data transfer process. Subsequently, some of the buffered data is maintained in some, but less than all, the segments of the buffer. Additionally, the maintained buffered data is indicated as VALID data. Thus, a subsequent process may be conducted directly using the data maintained in the buffer, and avoids moving the tape to reread the data.

Abstract: It is an object of the present invention to reduce a burden on a maintenance terminal of a storage control system. A storage control system 13 includes one or more operation information storages 59 in which operation information of the storage control system 13 is stored. Among plural DKAs 43 in the storage control system 13, a representative DKA 43D connected to the operation information storage 59 reads out operation information stored in an SM 39 and stores the operation information in the operation information storage 59. The operation information stored in the operation information storage 59 is outputted to an SVP 11 in a form in which the operation information is not stored in an HDD 7 of the SVP 11.

Abstract: Conventional methods for appending a validation code are not applicable to a disk array system in which the disk array comprises disk devices having a fixed sector length. The present invention solves this problem by separating validation codes from data blocks, bundling them together in blocks that can be easily matched with sectors, and carrying out all the associated management and control by hardware, such as coordination between validation codes and data blocks and operations of reading from and writing into the disk devices, thereby offering the same level of reliability as with conventional systems.

Abstract: A channel-based mechanism resolves race conditions in a computer system between a first processor writing modified data back to memory and a second processor trying to obtain a copy of the modified data. In addition to a Q0 channel for carrying requests for data, a Q1 channel for carrying probes in response to Q0 requests, and a Q2 channel for carrying responses to Q0 requests, a new channel, the QWB channel, which has a higher priority than Q1 but lower than Q2, is also defined. When a forwarded Read command from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, a Loop command is issued to memory by the first processor on the QWB virtual channel. In response to the Loop command, memory sends the written back version of the memory block to the second processor.