Patents Examined by Jonathan Fairbanks
  • Patent number: 5070475
    Abstract: A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.
    Type: Grant
    Filed: November 14, 1985
    Date of Patent: December 3, 1991
    Assignee: Data General Corporation
    Inventors: Kevin B. Normoyle, James M. Guyer, Rainer Vogt, Anthony S. Fong
  • Patent number: 4712174
    Abstract: A computer based system for generating text from a predetermined data base, in either prose or poetic form, in response to a plurality of input data provided by an operator in an interactive mode of operation with the computer. The preferred embodiment disclosed produces limerick style poetry in response to name, gender, geographic place of residence, primary and secondary traits and the number of syllables in certain input data items, and includes poetic material related to each of these data input items.
    Type: Grant
    Filed: April 24, 1984
    Date of Patent: December 8, 1987
    Assignee: Computer Poet Corporation
    Inventor: Jackson D. Minkler, II
  • Patent number: 4694420
    Abstract: An inverse assembly method for converting binary executable microprocessor code into corresponding assembly language mnemonics provides for the storage of all the possible binary codes and corresponding assembly language mnemonics in a plurality of tables set up in a decision tree form which corresponds to the format of a user document provided by the manufacturer of a target microprocessor. The instructions and data information contained within the executable code acquired from the taret microprocessor are distinguishably tagged prior to being stored in an acquisition memory. The code from the acquisition memory, in binary or hex form, indexes a primary table which contains a plurality of entries containing a binary value which may have a mask portion, each entry containing a plurality of actions having an optional string to be displayed, optional parameter masks and an optional table to call.
    Type: Grant
    Filed: December 23, 1985
    Date of Patent: September 15, 1987
    Assignee: Tektronix, Inc.
    Inventors: Mark E. Pettet, Gerd H. Hoeren