Patents Examined by Joni Richer
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Patent number: 10657700Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.Type: GrantFiled: November 1, 2017Date of Patent: May 19, 2020Assignee: Imagination Technologies LimitedInventors: Joseph M. Richards, Luke T. Peterson, Steven J. Clohset
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Patent number: 10642566Abstract: A media streaming device is provided. In one configuration, the media streaming device includes an interface for connecting the media streaming device to a display screen. A head mounted display (HMD) output for connecting to an HMD over a wireless connection provide by wireless communication circuitry. A processor for processing received video of interactive content. The processor is configured to format the video of interactive content for rendering on the display screen. A pass-through connection that is configured to interface the video of interactive content to the HMD via the HMD output over the wireless connection. The pass-through connection maintains a left-eye and right-eye format for rendering the video of interactive content in a three-dimensional format in the HMD.Type: GrantFiled: June 11, 2019Date of Patent: May 5, 2020Assignee: Sony Interactive Entertainment Inc.Inventors: Brian Watson, Anton Mikhailov, Jeffrey Stafford, Glenn Black
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Patent number: 10621109Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.Type: GrantFiled: February 27, 2019Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Kiran C. Veernapu
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Patent number: 10614615Abstract: A method of automatically tracking the portions of a 3D medical imaging volume, such as the voxels, that have already been displayed according to use-defined display parameters, notating those portions, and providing the user with information indicating what portions of the imaging volume have been displayed at full resolution.Type: GrantFiled: October 12, 2016Date of Patent: April 7, 2020Assignee: MERGE HEALTHCARE SOLUTIONS INC.Inventors: Evan K. Fram, Murray A. Reicher
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Patent number: 10606918Abstract: Embodiments of the present disclosure relate to a configurable convolution engine that receives configuration information to perform convolution or its variant operations on streaming input data of various formats. To process streaming input data, input data of multiple channels are received and stored in an input buffer circuit in an interleaved manner. Data values of the interleaved input data are retrieved and forwarded to multiplier circuits where multiplication with a corresponding filter element of a kernel is performed. Varying number of kernels with different sizes and sparsity can also be used for the convolution operations.Type: GrantFiled: October 25, 2019Date of Patent: March 31, 2020Assignee: Apple Inc.Inventors: Suk Hwan Lim, Junji Sugisawa, Muge Wang
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Patent number: 10600143Abstract: The present disclosure describes techniques for removing unnecessary processing stages from a graphics processing pipeline based on the format of data passed between the stages. Starting with a stage at a middle point in a pipeline, formats of data that are input to and output from the middle stage may be compared to each other. If the formats match, the middle stage may be removed from the pipeline. Thereafter, the format of data input to a pair of middle stages of the pipeline and output from the pipeline may be compared and, if they match, the middle pair may be deleted. This process may repeat until a middle pair is found where no match occurs between the input and output format. The remaining stages of the pipeline may be retained. In cases where a pipeline is not symmetrical, the formats of data at each node may be compared to each other.Type: GrantFiled: April 30, 2018Date of Patent: March 24, 2020Assignee: Apple Inc.Inventors: Aaron M. Ballow, Kenneth I. Greenebaum
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Patent number: 10599438Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.Type: GrantFiled: April 18, 2019Date of Patent: March 24, 2020Assignee: INTEL CORPORATIONInventors: Balaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Patent number: 10593287Abstract: Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing a representation to a connected device. An embodiment operates by recognizing a new device connected to a display device, collecting device fingerprint information from the new device, and requesting a device class representation information determined based on the device fingerprint information. Another embodiment operates by receiving device fingerprint information from a display device via a network connection, wherein the device fingerprint information is collected from a device connected to a display device, and providing device class representation information to the display device via the network connection, when the device class representation information corresponding to the device fingerprint information is available.Type: GrantFiled: December 1, 2017Date of Patent: March 17, 2020Assignee: Roku, Inc.Inventors: David Sharp, Jeff Bush, Jim Funk, Wim Michiels, Dale Luck
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Patent number: 10580112Abstract: Certain aspects of the present disclosure provide techniques for scalably and efficiently converting linear image data into multi-dimensional image data for multimedia applications. In one example, a method for managing image data includes receiving a line of image data in a linear format via a system bus of width T, wherein the image data's native format is a tile format of H lines per tile; forming H subsets of image data from the line of image data in the linear format; writing the H subsets of image data to a memory comprising BN=H banks of BW=T/BN pixel width, wherein each subset of the H subsets is written to a different bank of the BN banks; and outputting the H subsets of image data in the tile format.Type: GrantFiled: July 26, 2018Date of Patent: March 3, 2020Assignee: QUALCOMM IncorporatedInventors: Sandeep Nellikatte Srivatsa, Anish Kumar, Vikash Kumar, Ashish Mishra
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Patent number: 10565965Abstract: Embodiments of the present disclosure provide a method and a device for controlling a refresh rate of a mobile terminal and a mobile terminal. The method includes: determining that each of at least one foreground applications running currently is in a whitelist consisting of preset applications; obtaining a preset refresh rate corresponding to each of the at least one foreground application in the whitelist, and determining a target refresh rate of a display screen of the mobile terminal according to the preset refresh rate corresponding to each of the at least one foreground applications, in which an operation mode of the display screen is a command mode; and controlling the display screen by a display controller to read display frame data to be displayed from a frame buffer unit of the display screen at a frequency same as the target refresh rate and to display the display frame data.Type: GrantFiled: October 31, 2017Date of Patent: February 18, 2020Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.Inventors: Yongpeng Yi, Deliang Peng, Shengjun Gou, Xiaori Yuan, Gaoting Gan, Zhiyong Zheng, Hai Yang
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Patent number: 10565673Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.Type: GrantFiled: March 15, 2018Date of Patent: February 18, 2020Assignee: Intel CorporationInventors: Murali Ramadoss, Penne Lee, Ankur Shah, Ping Liu, Joseph Koston
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Patent number: 10558496Abstract: Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.Type: GrantFiled: January 8, 2018Date of Patent: February 11, 2020Assignee: INTEL CORPORATIONInventor: Michael Apodaca
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Patent number: 10529049Abstract: Techniques are provided herein for generating an integral image of an input image in parallel across the cores of a multi-core processor. The input image is split into a plurality of tiles, each of which is stored in a scratchpad memory associated with a distinct core. At each tile, a partial integral image of the tile is first computed over the tile, using a Single-Pass Algorithm. This is followed by aggregating partial sums belonging to subsets of tiles using a 2D Inclusive Parallel Prefix Algorithm. A summation is finally performed over the aggregated partial sums to generate the integral image over the entire input image.Type: GrantFiled: March 27, 2017Date of Patent: January 7, 2020Assignee: Oracle International CorporationInventors: Venkatanathan Varadarajan, Arun Raghavan, Sam Idicula, Nipun Agarwal
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Patent number: 10522114Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.Type: GrantFiled: May 30, 2018Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Jeffery S. Boles, Hema C. Nalluri, Balaji Vembu, Michael Apodaca, Altug Koker, Lalit K. Saptarshi
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Patent number: 10516812Abstract: Techniques for selective display frame fetching can include receiving or fetching rendered display frames by a display engine. The display engine can determine if a new frame includes one or more dirty portions. If the new frame includes one or more dirty portions, just the dirty portions can be loaded by the display engine into a display buffer. The display engine can also scan out just the dirty portions from the display buffer to a display.Type: GrantFiled: April 2, 2018Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Jason Tanner, Paul Diefenbaugh, Vishal Sinha, Arthur Runyan, Gary K. Smith, Kathy Bui, Yifan Li, Shirley Huang Meterelliyoz
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Patent number: 10510317Abstract: Embodiments described herein provide for a display system to generate and display data on a display device, the display system comprising one or more graphics processors to generate one or more frames of data for display on the display device; display logic to receive a request to display the one or more frames of data, the request including a requested presentation time in which the one or more frames of data are to be displayed; and a display engine to present the one or more frames of data to the display device for display at a target presentation time, the target presentation time derived from the requested presentation time, wherein the display engine is to adjust a refresh rate of the display device based on the target presentation time of the one or more frames of data.Type: GrantFiled: September 23, 2016Date of Patent: December 17, 2019Assignee: Apple Inc.Inventors: Arthur L. Spence, Jeremy T. Sandmel, David M. Chan, Chendi Zhang, Peter C. Tsoi
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Patent number: 10510175Abstract: The present disclosure provides example methods for changing graphics processing resolution according to a scenario. In one example, a first display scenario is determined as a scenario in which energy can be saved. Based on the determination, a graphics processing resolution of a graphics processor can be reduced. At least one target graphics frame in the first display scenario can be rendered by the graphics processor according to the reduced graphics processing resolution to obtain at least one target image frame. The at least one target image frame can be adapted according to screen display resolution, and the at least one adapted target image frame can be displayed. The present disclosure further provides a portable electronic device and a system for changing graphics processing resolution according to a scenario.Type: GrantFiled: December 3, 2015Date of Patent: December 17, 2019Assignee: Huawei Technologies Co., Ltd.Inventor: Jianbin Qiu
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Patent number: 10504480Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.Type: GrantFiled: May 18, 2017Date of Patent: December 10, 2019Assignee: Google LLCInventors: Albert Meixner, Neeti Desai, Dilan Manatunga, Jason Rupert Redgrave, William Mark
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Patent number: 10496579Abstract: Graphics processing unit (GPU) with sensor interface. In an exemplary embodiment, an apparatus includes a GPU that includes a host interface to communicate with a host central processing unit (CPU), a sensor interface to communicate over a sensor bus, and a sensor connected to the sensor bus. The sensor communicates sensor data through the sensor interface, so that the sensor data does not flow through the host interface to the GPU. In an exemplary embodiment, a method is provided for operating a GPU having a host interface to communicate with a host CPU and a sensor interface. The method includes sending control signaling through the sensor interface to control a sensor to capture sensor data, and acquiring the sensor data sent from the sensor through the sensor interface. The sensor data does not flow through the host interface to the GPU.Type: GrantFiled: November 13, 2017Date of Patent: December 3, 2019Inventor: Bobby Gene Burrough
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Patent number: 10489478Abstract: Embodiments of the present disclosure relate to a configurable convolution engine that receives configuration information to perform convolution or its variant operations on streaming input data of various formats. To process streaming input data, input data of multiple channels are received and stored in an input buffer circuit in an interleaved manner. Data values of the interleaved input data are retrieved and forwarded to multiplier circuits where multiplication with a corresponding filter element of a kernel is performed. Varying number of kernels with different sizes and sparsity can also be used for the convolution operations.Type: GrantFiled: November 27, 2017Date of Patent: November 26, 2019Assignee: Apple Inc.Inventors: Suk Hwan Lim, Junji Sugisawa, Muge Wang