Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Abstract: The invention relates to an organic light-emitting diode (OLED) system comprising a multi-layered structure having at least two reflective interfaces, and a semiconducting organic layer sandwiched between first and second electrodes; wherein at least one of the reflective interfaces is semi-transparent to form a microcavity in between the two reflective interfaces; wherein a layer is provided in the microcavity between an electrode and a reflective interface that is formed of a photoactive birefringent material; and wherein the photoactive birefringent material is selectively activated.

Abstract: Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation.

Abstract: The present invention relates to a white light emitting device having high color rendering, and the white light emitting device is a white light emitting lamp comprising a blue LED chip having an excitation wavelength of 440-460 nm, and a phosphor layer covering a light emitting surface of the blue LED chip and excited by the excitation wavelength of the blue LED chip so as to emit light, wherein the phosphor layer comprises a first phosphor having an emission peak wavelength of 480-499 nm; a second phosphor having an emission peak wavelength of 500-560 nm; and a third phosphor having an emission peak wavelength of 600-650 nm. According to aspects of the present invention, a white LED chip having high color rendering can be provided, and particularly, the white light emitting device having high color rendering for specific colors such as R9 and R12 can be provided.

Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The BSI image sensor includes a semiconductive substrate, a deep trench isolation (DTI) at a back side of the semiconductive substrate, and a dielectric layer. the dielectric layer includes a top portion over the back side, and a side portion lined to a sidewall of the DTI. The BSI image sensor includes a planarization stop layer disposed conformally on top of the dielectric layer. The planarization stop layer includes a top section on the top portion, a side section lined against the side portion, and a first transmittance. The BSI image sensor includes a low-transparent material inside the DTI, and the low-transparent material includes a second transmittance. The second transmittance is lower than the first transmittance.

Abstract: A composite substrate has a carrier and a utility layer. The utility layer is attached to the carrier by means of a dielectric bonding layer and the carrier contains a radiation conversion material. Other embodiments relate to a semiconductor chip having such a composite substrate, a method for producing a composite substrate and a method for producing a semiconductor chip with a composite substrate.

Abstract: A semiconductor device connection structure includes: a semiconductor element having a plate shape and including an external connection electrode on a surface of the semiconductor element; a support member which is stacked on the semiconductor element to be adhered to the semiconductor element and of which adhesion surface has a column shape that is substantially same as that of the semiconductor element, a thickness of the support member in a stacking direction being larger than that of the semiconductor element; and a flexible board configured to be electrically connected to the external connection electrode. The flexible board is arranged on a side surface of the semiconductor element and on a side surface of the support member and is adhered only to the side surface of the support member with an adhesive.

Abstract: An NLDMOS device that includes a drift region, a P well, and a first PTOP layer and a second PTOP layer formed on the drift region, wherein the first PTOP layer has the same lateral size with the second PTOP layer, the first PTOP layer is spaced from the second PTOP layer in the longitudinal direction and located on the bottom of the second PTOP layer, with the depth of the first PTOP layer less than or equal to that of the bottom of the P well. The present invention also discloses a method for manufacturing the NLDMOS device.

Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Abstract: An integrated circuit package and a method of fabrication of the same are introduced. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.

Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

Abstract: An organic electroluminescent display device is provided. The display device has a polarizing film disposed at a light exiting side thereof. The polarizing film has a plurality of polarization units, and adjacent polarization units have different polarization directions.

Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a first gate structure formed across the fin structure. The semiconductor structure further includes a first source/drain structure formed in the fin structure adjacent to the first gate structure and a first contact formed over the first source/drain structure. In addition, the first contact includes a first extending portion extending into the first source/drain structure.

Abstract: A monolithic active pixel radiation detector including a method of fabricating thereof. The disclosed radiation detector can include a substrate comprising a silicon layer upon which electronics are configured. A plurality of channels can be formed on the silicon layer, wherein the plurality of channels are connected to sources of signals located in a bulk part of the substrate, and wherein the signals flow through electrically conducting vias established in an isolation oxide on the substrate. One or more nested wells can be configured from the substrate, wherein the nested wells assist in collecting charge carriers released in interaction with radiation and wherein the nested wells further separate the electronics from the sensing portion of the detector substrate. The detector can also be configured according to a thick SOA method of fabrication.

Abstract: A display device includes a first substrate, a pixel defining layer on the first substrate, the pixel defining layer configured to define a light emission area, a first electrode in the light emission area, a light emitting layer on the first electrode, a second electrode on the light emitting layer, a second substrate which is opposite to the first substrate, and a reflecting member on a lower surface of the first substrate. The reflecting member may include a first reflecting unit on the lower surface of the first substrate, the first reflecting unit having an aperture at a position overlapping the light emission area, and a second reflecting unit on the first reflecting unit.

Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

Abstract: A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

Abstract: The present application discloses an organic light emitting diode comprising a cathode; an anode; a plurality of light emitting layers connected in series between the cathode and the anode; and a charge generation layer between at least one pair of adjacent light emitting layers. At least one light emitting layer comprises a host layer having charge transport property.

Abstract: A semiconductor structure comprising a first layer, a metal layer and a second layer is disclosed. The first layer comprises a recessed surface. The metal layer is above a portion of the recessed surface. The second layer is above the metal layer and confined by the recessed surface. The second layer comprises a top surface, a first lateral side and a second lateral side. The etch rate of an etchant with respect to the metal layer is greater than the etch rate of the etchant with respect to the second layer. The thickness of the second layer in the middle of the second layer is less than the thickness of the second layer at the first lateral side or the second lateral side. A method of forming a semiconductor structure is disclosed.