Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes an array area and a peripheral area adjacent to each other, and the array area includes a buffer area connected to the peripheral area; forming a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, on the substrate, forming a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, in the buffer area; removing the third dielectric layer through a wet etching process; and etching the second supporting layer in the peripheral area after removing the third dielectric layer.

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

Abstract: A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.

Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Abstract: A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.

Abstract: The present invention relates to a method for coating a photovoltaic panel, and a photovoltaic power generating device using same and, more specifically, to a method for coating a photovoltaic panel, and a photovoltaic power generating device using same, wherein the method inhibits various pollutants such as dust and salt from attaching to the surface of a photovoltaic panel so as to increase power generation efficiency.

Abstract: Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a <hk0>, <h00>, or <0k0> direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

Abstract: An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate includes an array region and a peripheral region adjacent to each other, and the array region includes a buffer region connected with the peripheral region; a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, are formed on the substrate; a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, is formed in the buffer region; the third dielectric layer is removed through a wet etching process; and the second supporting layer in the peripheral region is etched after the third dielectric layer is removed.

Abstract: A plasma processing system includes a control device. The control device executes raising a lifter to deliver a cover ring supporting an edge ring to the lifter; moving a jig supported by a holder to a space between the cover ring and a substrate support surface/an annular support surface; raising a different lifter to deliver the jig to the different lifter; extracting the holder, and then moving the lifter and the different lifter relatively to deliver the edge ring to the jig; lowering only the lifter to deliver the cover ring to the annular member support surface; moving the holder to a space between the cover ring and the jig, and then lowering the different lifter to deliver the jig to the holder; and extracting the holder from the processing chamber to transfer the jig supporting the edge ring from the processing chamber.

Abstract: A semiconductor structure, a preparation method of the same, and a semiconductor device are provided. The semiconductor structure includes a substrate, including an active area. A first electrode layer is arranged on the substrate and electrically connected to the active area. The first electrode layer extends in a direction perpendicular to the substrate. A dielectric layer is arranged on a surface of the first electrode layer. A second electrode layer is arranged on a surface of the dielectric layer. Each of the surface of the first electrode layer and the surface of the dielectric layer are provided with an uneven structure.

Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.

Abstract: A laminated capacitor and a method for manufacturing the same are provided. The method includes operations of providing a substrate; forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads on the substrate; forming a sub-capacitor structure on the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and repeatedly performing an operation of forming a connection structure and the sub-capacitor structure for N times on the sub-capacitor structure, such that N connection structures and N+1 sub-capacitor structures are alternately arranged along a direction perpendicular to the substrate, wherein N is an integer greater than or equal to 1.

Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Abstract: A manufacturing method of a capacitive structure includes: providing a semiconductor base; forming a first mask layer on the semiconductor base, the first mask layer having a plurality of first round hole patterns distributed uniformly; forming first openings distributed uniformly on the semiconductor base by etching based on the first round hole patterns; forming a second mask layer on one side, away from the semiconductor base, of the first openings, and forming a plurality of second round hole patterns on the second mask layer; forming second openings distributed uniformly on the semiconductor base by etching based on the second round hole patterns, and meanwhile continuously etching the first openings; and etching the first openings and the second openings to form capacitive holes, and depositing a lower electrode layer, a dielectric layer and an upper electrode layer within the capacitive holes to form the capacitive structure.