Abstract: Embodiments of the present application disclose a capacitor and a method for producing a capacitor. The capacitor includes: an electrode layer including a first electrode and a second electrode separated from each other; a laminated structure including n dielectric layer(s) and n+1 conductive layers, where the n dielectric layer(s) and the n+1 conductive layers form a structure that a conductive layer and a dielectric layer are adjacent to each other, and the laminated structure forms at least two columnar structures, and n is a positive integer; and an interconnection structure configured to electrically connect an odd-numbered conductive layer in the n+1 conductive layers to the first electrode and electrically connect an even-numbered conductive layer in the n+1 conductive layers to the second electrode. According to the technical solution of the embodiments of the present application, capacitance density of the capacitor could be improved.

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

Abstract: In an IPS-mode liquid crystal display device, the area of a terminal portion is decreased. A liquid crystal display device includes a TFT substrate and a counter substrate attached to the TFT substrate with a sealing material, and includes a display region and a terminal portion formed on the TFT substrate. A shielding transparent conductive film is formed on the outer side of the counter substrate. On the terminal portion, an earth pad formed with a transparent conductive film is formed on an organic passivation film. The shielding transparent conductive film is connected to the earth pad through a conductor. Below organic passivation film of the terminal portion, a wire is formed.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a semiconductor layers and a silicide layer. The insulating layer is formed on the semiconductor substrate. The semiconductor layer is formed on the insulating layer and includes a polycrystalline silicon. The silicide layer is formed on the semiconductor layer. The semiconductor layer has a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The second semiconductor part is adjacent the second semiconductor region. In a width direction of the first semiconductor part, a second length of the second semiconductor part is greater than a first length of the first semiconductor part. A distance between the first and second semiconductor regions is 100 nm or more in an extension direction in which the first semiconductor region extends.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.

Abstract: A method includes providing a semiconductor substrate, and forming a first N-type implant region and a second N-type implant region in the semiconductor substrate. The first N-type implant region and the second N-type implant region are separated by a portion of the semiconductor substrate. The method also includes forming a first P-type implant region in the semiconductor substrate, and performing a heat treatment process on the semiconductor substrate to form an N-type well region and a P-type well region in the semiconductor substrate. The N-type well region has a first portion, a second portion, and a third portion between the first portion and the second portion. The doping concentration of the third portion is lower than the doping concentration of the first portion and the doping concentration of the second portion.

Abstract: The characteristic of Fe-doped HEMTs is improved. The invention provides a nitride semiconductor substrate having a substrate, a buffer layer made of nitride semiconductors on the substrate, and an active layer composed of nitride semiconductor layers on the buffer layer; the buffer layer containing Fe, the Fe having a concentration profile in which the Fe concentration increases monotonically and gradually in the thickness direction of the buffer layer from an interface between the substrate and the buffer layer, has a maximum value within 2×1017 to 1.1×1020 atoms/cm3 inclusive, and decreases monotonically and gradually toward an interface between the buffer layer and the active layer, and the point of the maximum value being within ±50 nm from the midpoint in the thickness direction of the buffer layer, and being 500 nm or more away from the interface between the buffer layer and the active layer.

Abstract: A Schottky barrier diode includes a substrate, a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer, and a metal layer formed on the second semiconductor layer to form a Schottky barrier, wherein the first semiconductor layer and the second semiconductor layer are formed of different materials, and a conduction band offset between the first semiconductor layer and the second semiconductor layer is less than a set value.

Abstract: An image sensing device is provided to include a pixel array including unit pixel blocks. Each of the unit pixel blocks includes a first subpixel block including a first floating diffusion (FD) region and unit pixels surrounding the first FD region, a second subpixel block including a second FD region electrically coupled to the first FD region and unit pixels surrounding the second FD region. The image sensing device also includes a first pixel transistor array and a second pixel transistor array that are disposed at opposite sides of the first subpixel block in the first direction. The first and the pixel transistor array include a first drive transistor set and a second drive transistor set, respectively.

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Abstract: A display substrate, display panel, and method of fabricating the display substrate. The display substrate includes: a first thin film transistor on a substrate; a second thin film transistor on the substrate and on the same side of the substrate as first thin film transistor; a light blocking structure between the substrate and an active region of first thin film transistor. The light blocking structure is configured to block at least a portion of light incident on the active region of first thin film transistor, such that a ratio of area of an illuminated portion of the active region of first thin film transistor to an area of the active region of first thin film transistor is less than a ratio of area of an illuminated portion of an active region of second thin film transistor to an area of the active region of second thin film transistor.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: A semiconductor device includes a semiconductor substrate; a vertical Hall element including a magnetosensitive portion, and formed in the semiconductor substrate; and an excitation wiring provided above a surface of the semiconductor substrate and apart from the magnetosensitive portion. The excitation wiring is formed of a single wiring with a plurality of turns. The excitation wiring includes a plurality of main wiring portions arranged side by side, and apart from one another in an overlapping region that overlaps the magnetosensitive portion as viewed in plan view from a direction orthogonal to the surface of the semiconductor substrate; and auxiliary wiring portions connecting each of the plurality of main wiring portions to one another in series.

Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: A method for forming a solar cell including steps of (1) providing a semiconductor wafer having an upper surface; (2) applying an electrical contact material to the upper surface, the electrical contact material forming an electrically conductive grid that includes grid lines extending from a bus bar; (3) forming an isolation channel in the semiconductor wafer to define a solar cell portion and a wing portion, wherein the wing portion is electrically isolated from the solar cell portion, and wherein the wing portion is substantially free of the electrical contact material; (4) submerging the semiconductor wafer in a solvent, wherein formation of metal dendrites on the grid lines of the electrically conductive grid is inhibited; and (5) separating the solar cell portion from the wing portion.

Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a P-type vertical field effect transistor (VFET) including a first channel region and a first top source/drain region sequentially stacked on a substrate in a vertical direction, an N-type VFET including a second channel region and a second top source/drain region sequentially stacked on the substrate in the vertical direction, and a top contact layer contacting both the first top source/drain region and the second top source/drain region.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.

Abstract: A semiconductor device including a first electrode on a substrate, a second electrode on the first electrode, a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode, a second dielectric layer between the second electrode and the third electrode, and a first contact plug penetrating the third electrode and contacting the first electrode, the first contact plug contacts a top surface of the third electrode and a side surface of the third electrode.