Abstract: A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends floating point data to a reduction mechanism, and the reduction mechanism computes the sums only for a group of which exponent sections have a highest value and a group of which exponent sections have a second highest value, and adds the sum of the group of which the exponent sections have a highest value and the sum of the group of which the exponent sections have a second highest value. By this, the consistency of the computation result can be guaranteed even if the sum is computed regardless the computing sequence of the values.

Abstract: A method and apparatus are provided for mixing a plurality of signals within a predetermined dynamic range without clipping. In the method and apparatus, first and second signal samples are added together to obtain a first intermediate result. Then the first signal sample is multiplied with the second signal sample to obtain a second intermediate result. In one embodiment, the second intermediate result is subtracted from the first intermediate result to obtain a third intermediate result, and the third intermediate result is discarded if the third intermediate result is less than zero. In another embodiment, the second intermediate result is added to the first intermediate result to obtain the third intermediate result, and the third intermediate result is discarded if the third intermediate result is greater than zero. An output signal sample is provided based on the third intermediate result.

Abstract: Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of ?2, ?1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second bit that is true when the associated number is ?2, a third bit that is true when the associated number is either negative or zero, and a fourth bit that is true when the associated number has an absolute value of 1.

Abstract: Method to convert a hexadecimal floating point number (H) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply add with an A-register a B-register for two multiplicand operands and a C-register for an addend operand, wherein a leading zero counting unit (LZC) is associated to the addend C-register, wherein the difference of the leading zero result provided by the LZC and the input exponent (E) is calculated by a control unit and determines based on the Raw-Result-Exponent a force signal (F) with special conditions like ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’.

Abstract: The invention provides an apparatus and a method for performing a calculation operation with at least one input signal consisting of signal sections, wherein each signal section of said input signal has a constant amplitude. The apparatus comprises a signal transformation unit for transforming at least one input signal into a first intermediary signal having a virtual amplitude with respect to at least one carrier signal. The calculation unit is provided for performing the calculation operation on said first intermediary signal to generate a second intermediary signal. A signal re-transformation unit re-transforms the second intermediary signal into an output signal consisting of signal sections, wherein each signal section of said output signal has a constant amplitude.

Abstract: The common concurrency runtime (CCR) provides a simple and self-consistent set of concurrency primitives that developers can use to more readily split their computation into more discrete chunks that can scale better with additional processors. This set of primitives provides for very scalable applications that are well suited for the coming world of ubiquitous communication and very large scale out for the number of local processors. The CCR may be implemented as a single library in C# that implements channels with input and asynchronous output capabilities, along with an atomic test-and-input primitive. On top of this, richer derived operators (e.g., choice, join, replication, reader-writers, scatter-gather, etc.) may be encoded. Thus, existing C# may be built upon to provide the capability to concurrently issue I/O requests to remote systems while simultaneously performing other functions locally to increase the efficiency of the distributed system.

Abstract: Systems, methods and apparatus are provided through which in some embodiments, domain knowledge is translated into a knowledge-based system. In some embodiments, a formal specification is derived from rules of a knowledge-based system, the formal specification is analyzed, and flaws in the formal specification are used to identify and correct errors in the domain knowledge, from which a knowledge-based system is translated.

Abstract: An intermediate representation of sequences of instructions for a stacked based computer is a code graph using a numbering method on the nodes of the graph, along with a set of relations among the nodes, to determine, in a single pass, the independence of each node or sub-graph represented by the node. The numbering is a post-order that directly, by numerical comparison defines the relevant hierarchical relationships among sub-graphs. The sub-graph of a particular node may have one or more alias nodes that refers to target nodes, a target node being a node representing an argument which is the result of a previous program instruction. For a subgraph to be considered independent, any aliases generated by nodes within the subgraph must themselves be contained in it, and conversely, any aliases in the subgraph must have been generated by nodes also within it.

Abstract: Systems, methods and apparatus are provided through which in some embodiments an informal specification is translated without human intervention into a formal specification. In some embodiments the formal specification is a process-based specification. In some embodiments, the formal specification is translated into a high-level computer programming language which is further compiled into a set of executable computer instructions.

Abstract: The present invention performs a lossless four-point orthogonal transformation with reduced rounding errors using a simple configuration. A data transformation apparatus receives four items of vector data X0, X1, X2, and X3, ( Y 0 Y 1 Y 2 Y 3 ) = 1 1 + a 2 ? ( 1 a a a 2 a - 1 a 2 - a a a 2 - 1 - a a 2 - a - a 1 ) ? ( X 0 X 1 X 2 X 3 ) and determines D0 to D3 as: D0=X0+aX1+aX2+a2X3; D1=aX0?X1+a2X2?aX3; D2=aX0+a2X1?X2?aX3; and D3=a2X0?aX1?aX2+X3. Integer data smaller than half a divisor {1+a2} is added to D1 to determine D1?, and a value equal to half the divisor is added to D0, D2, and D3 to determine D0?, D2?, and D3?, respectively. D0?, D1?, D2?, and D3? are divided by the divisor and the results are rounded such that resulting integers are smaller than the results of division, and outputting the resulting integers.