Abstract: A virtual storage address space access control system has an access register having a plurality of access register numbers, a dynamic address translation unit and translation lookaside buffer for translating a virtual address to a real address by using a segment table designation. It further comprises first and second control registers for designating primary and secondary spaces, respectively, the primary and secondary spaces being accessed when the content of the access register is "1" or "0". Also included are access register translation lookaside buffer for indirectly obtaining a segment table designation by using a content of the access register and access register auxiliary translation lookaside buffer for directly obtaining the segment table designation by using the access register number.

Abstract: A computer using virtual memory management employs a random-access type storage device such as a semiconductor memory for page swapping. The semiconductor memory is formatted to provide multiple partitions of varying block size, e.g., two block sizes, for compressed pages, and another block size for uncompressed original-sized pages. The data to be stored is in pages of fixed size, and these pages are compressed for storage if the compressed size fits in the block size of one of the small-block partitions in the memory. If a data page is not compressible to one of the small block sizes, it is stored uncompressed in the other full-size partition. The operating system maintains a table storing the locations of the pages in the partitions, so upon recall the page (if compressed) is retrieved from its location found using the table, decompressed and sent to the CPU. The relative number of blocks in the partitioned memory (e.g.

Abstract: A storage controller having additional cache memory and a system for recovering from failure and reconfiguring a control unit thereof in response thereto. The inventive controller includes a first cluster for directing data from a host computer to a storage device and a second cluster for directing data from a host computer to a storage device. A first cache memory is connected to the first cluster and a second cache memory is connected to the second cluster. A first nonvolatile memory is connected to the second cluster and a second nonvolatile memory is connected to the first cluster. Data is directed to the first cache and backed up to the first nonvolatile memory. The second cache is similarly backed up by the second nonvolatile memory. In the event of failure of the first cache memory, data is directed to the second cache and backed up in the second nonvolatile memory.

Abstract: A method of and apparatus for extending the memory capacity of a computer system having a rotating optical memory storage device and a fixed memory storage includes a scanner for accessing computer information and a rotating optical read-write memory device for storing computer information and for accessing and transferring computer information to and from the scanner and to and from the discrete memory storage of the computer system. The method includes the steps of storing computer information on a scannable storage medium, accessing computer information from the scannable storage medium, and transferring the computer information to the scannable storage medium or discrete memory storage of the computer system through the use of a multi-head rotating optical memory device. The scanner uses an optical laser scanning system to encode computer information on a physical medium. The rotating optical memory device uses virtual memory techniques to store and retrieve data for use at a required time.

Abstract: A dual disk drive peripheral data storage system is disclosed. The dual disk drive is a combination of a hard disk drive and a solid state disk drive whereby the solid state buffer memory that is typically used as a data cache for the hard disk drive is partitioned such that one portion provides the memory for the solid state disk drive while another portion remains as the cache for the hard disk. The dual disk drive provides the capability for a user to repartition the solid state buffer memory such that the sizes of the solid state disk drive memory and cache memory can be adjusted to increase the data transfer rate with a host computational system.

Abstract: A random access memory (RAM) complex that can concurrently read and write to different addresses. The memory complex includes two RAMs, each having an address selector, includes a data out multiplexer for selecting outputs from one of the RAM's. A tag array stores an array of tag, one for each address in the RAM's. The tag marks which one of the two RAM's has the valid data for the corresponding read address. During a concurrent read and write cycle, the tag selects the read address for one RAM, selects the write address for the other RAM and a staged copy of the tag controls the multiplexer to select data from the correct RAM for the data out.

Abstract: The removable media management system operates with a manual, an automated, or a combination of subsets of manual and automated library system to store and retrieve media cartridges for an associated plurality of drive elements. This system enables the use of a plurality of types of media within the single monolithic cartridge library system and a corresponding plurality of drive elements associated with said library system. Thus, each drive element has associated therewith a number of object storage locations within the library system which contains media of a form and content that matches the drive element. The removable media management system maps the correspondence between object storage location, media type, designated drive element in a manner such that the single library is partitioned into subsets for the user, i.e.

Abstract: A full set of 36 EMS registers is provided for a computer, without using any of the registers located in the 256K to 640K address range of the standard RAM. This is accomplished by providing first and second alternate RAM sets of 12 registers each, which are accessed in the same 768K to 960K space as the standard twelve registers located in the 768K to 960K space. Access to the 24 registers in the first and second alternate sets of registers is controlled by two control bits. These bits translate address signals directed to the 768K to 960K space to be directed to one or the other of the first and second alternate sets of 12 registers; so that the alternate registers are accessed in the same space as the standard 12 registers in this 768K to 960K space.

Abstract: A solid state data recorder employs a solid state memory to record data in the form of data words of variable length transmitted to the memory on a flexible width data bus. The memory is monitored to determine failed memory locations, and such locations are mapped out so as not to be used to store data. Bus lines are selected lines in accordance with mapped out memory locations in order to transfer the variable length data words to and from the memory. By employing the variable length data words and flexible width data bus, loss of useable recording space in the memory is very gradual, thus minimizing the amount of spare memory area required.

Abstract: An output control method includes the step of outputting a predetermined portion of data obtained by first direct memory access as last data of one line, checking whether the data obtained by the access includes data other than the last data, performing direct memory access again with respect to data at the same address as that in the previous access as start data of a line next to the previous line when it is determined that the obtained data includes data other than the last data, and outputting a predetermined portion of the data obtained by the second access as the start data. An output control apparatus for this method is also disclosed.

Abstract: Computer-based application systems encounter a case in which data must not exist in a plurality of storage devices. This problem emerges typically in translocating data. The invention disclosed here is intended to erase data in its original location promptly after it has been translocated. The invention comprises a memory card containing a processor and a storage device wherein the memory card is connected to an external processing apparatus. In response to a command issued by the processing apparatus, data is erased from the memory card just after it is copied to the processing apparatus. Thereafter, the data stored in the processing apparatus may be transferred to a second memory card.

Abstract: The improved cache system reduces the effects of latency times by utilizing a preload instruction inserted by the compiler into the code. The preload instruction is sent sufficiently in advance of the corresponding load instruction to guarantee that the relevant data is in the cache memory when the load instruction is received. In addition, the invention prevents the pollution of the cache with data that will only be used once during the expected lifetime of the data in the cache. This second feature of the invention assures that a large number of references to data that will only be used once does not result in the contents of the cache being replaced with the subsequent need to reload the contents after the data references have been completed.

Abstract: A disc controller, which is connected to a plurality of channels for supplying access requests and discs. The controller includes a plurality of storage paths which control transfer of data between a cache, the channels and the discs, and a control memory which controls the respective operations of the plurality of storage paths. The control memory stores information which is used to select a storage path in accordance with predetermined standards for storage path selection. A disc or the cache is accessed using the selected storage path.

Abstract: An electronic filing apparatus for filing and retrieving document data in a disk storage medium. The apparatus includes an image reading part for scanning a document with plural pages to successively generate image data from each of the pages of the document, first and second buffer memories in which the image data generated by the image reading part is temporarily stored, a first recording part for temporarily recording the image data on a hard disk in the first recording part, a first control part for temporarily storing the image data in either the first buffer memory or the second buffer memory in proper sequence, a second recording part for recording the image data on an optical disk in the second recording part, and a second control part for recording and registering the image data on the hard disk into the optical disk at an idle time after the recording of the image data on the hard disk is completed.

Abstract: The provision of a flash memory, virtual mapping system that allows data to be continuously written to unwritten physical address locations. The virtual memory map relates flash memory physical location addresses in order to track the location of data in the memory.

Abstract: A DMA controller, has bus switching means for connecting certain data bus signals with other data bus signals by itself during the DMA bus cycle. Therefore, even if the data bus signals in which a memory is connected are different from the data bus signals in which an I/O device is connected, these data bus signals can be connected with each other through said bus switching means, without using an external bus switching device.

Abstract: An execution control system for use in a pipeline instruction execution control type information processing device, wherein an instruction interval is executed sequentially after completion of a certain instruction used in, for example, a debugging process and before reading out a next instruction. The execution control system is part of an information processing device which has a pipeline instruction execution control portion. The instruction execution control system has a program status word holding unit for holding a program status word. The program status word includes information indicating whether or not an instruction interval is to be sequentially executed as well as information indicating execution status of a program. The instruction execution control system also has an instruction execution sequencing indicating unit which indicates to the instruction execution control portion whether or not the instructions in the instruction interval are to be sequentially executed.

Abstract: The invention assures data consistency at a time of data update. Also, the invention results in a reduction in the access time required to store incoming data. In response to an equality signal from a comparator circuit of a write buffer circuit which is then in an active level, data is immediately read out from a data buffer store having an address corresponding to the equality signal. A unidirectional tristate buffer is provided for temporarily disconnecting an address bus extending between a CPU and the write buffer circuit, again when such equality signal is in an active level. Similarly, a bidirectional tristate buffer is provided for temporarily disconnecting a data bus extending between the CPU and the write buffer circuit. At times a local controller may take over command of buffer storage of data, with an interrupt of the local controller if the central processor seizes command.

Abstract: Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A substantially larger external cache array is coupled to both the CPU and the CC via first, integrated address and data bus. The CC is in turn coupled to a second bus interconnecting, among other devices, processors, I/O devices, and a main memory. The external cache is subblocked. A cache directory in the CC tracks usage of the external cache. An input buffer in the CC is connected to the first bus to provide buffering of commands sent by the CPUs. An output buffer in the CC is coupled to the second bus for buffering commands directed by the CC to devices operating on the second bus.

Abstract: A method and a computer program for performing the method are disclosed for optimizing signals being exchanged between a host unit and an addressable-buffer peripheral device. The program optimizes an outgoing signal from the host unit by (1) creating an updated-state map representing the state of the peripheral device buffer expected to exist after processing by the peripheral device of the outgoing signal, (2) performing an exclusive-or (XOR) operation using the updated-state map and a present-state map representing the existing state of the buffer, and (3) constructing and transmitting a substitute outgoing signal which represents only changes to the buffer, and in which all premodified field flags are turned off. Position-dependent characters, such as attribute bytes are translated into nondata characters prior to incorporation into a map, and are retranslated into their original form for use in the substitute signal.