Abstract: Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal and an output. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal and an output may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs.

Abstract: A computer-readable recording medium stores a program causing a computer to determine the size of an applied 2N-branch non-contact Huffman tree depending on where in a range the total number of types (X) of character information groups exists. The size of the 2N-branch non-contact Huffman tree has the maximum number of branches, 2N. The radicand N is an upper limit of the length of a compression code. Thus, when the size of the 2N-branch non-contact Huffman tree is determined, the radicand (N) may be determined depending on the total number of types (X) of character information groups. Specifically, when the total number of types (X) of character information groups is 2x?2<X?2x?1, if the maximum number of branches (2N) is at least 2x?1, a Huffman tree can be established. To minimize the size, N=x?1 may be adopted. Further, when the total number of types (X) of character information groups is 2x?1<X?2x, if the maximum number of branches (2N) is at least 2x, a Huffman tree can be established.

Abstract: The present invention generally relates to storing sequence read data. The invention can involve obtaining a plurality of sequence reads from a sample, identifying one or more sets of duplicative sequence reads within the plurality of sequence reads, and storing only one of the sequence reads from each set of duplicative sequence reads in a text file using nucleotide characters.

Abstract: A phase conversion device, which converts an electromagnetic wave into a right-handed circularly polarized wave and a left-handed circularly polarized wave to attenuate electric and magnetic effects, includes first, second, and third layers. The first layer includes a ½ lambda wavelength plate. The second layer includes a ¼ lambda wavelength plate. The third layer includes a ½ lambda wavelength plate. The device is effective to reduce an influence of the electromagnetic wave on an electric field and a magnetic field. The device may be portable and useable to reduce an influence of electromagnetic waves on a human body.

Abstract: Disclosed is a feed forward sigma-delta analog to digital conversion (ADC) modulator. The disclosed structure combines feedback circuit, adder circuit and quantization circuit, and has advantages of high stability, without active circuit, and using successive approximation register (SAR) control circuit, thus realizes the function of multi-bit quantization by using only one comparator.

Abstract: A signal gate is provided where the gate can be low impedance to allow a signal to pass or be high impedance to block it. The signal gate has two output nodes arranged such that during the blocking mode spurious signals passing through the gate by way of parasitic components are presented as common mode signals at the output nodes.

Abstract: An information processing device compares a particular unit including a plurality of words and each word corresponding to an encoded output previously output to an output buffer, when encoding an input text word by word and outputting the encoded input text to an output buffer, detects a duplicating part that includes the particular unit and performs dynamic encoding on the detected part to replace the detected part with a dynamic code.

Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Abstract: A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j?1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.

Abstract: A mechanism is disclosed to dismantle/erect a portable antenna that includes a linkage between radial driven elements and radial ground plane elements of the antenna which acts to cause them to move together between a collapsed and an erect arrangement.

Abstract: A system and method to achieve low power and/or low supply operation of a delta-sigma modulator by taking advantage of the inherent virtual ground of the delta-sigma loop to make the input to a low power integrator small and largely independent of the input signal. This results in improved linearity of the integrator and relaxed constraints on the supply for the first stage integrator. The architecture also enables direct access to the quantization error of the feedback loop and thus can be used to either/or: 1. Calibrate the modulator, 2. Achieve reduced quantization noise, 3. Stabilize the loop by compensating for excess loop delay. Low voltage common-mode-feedback is also achieved using the techniques described.

Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

Abstract: Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.

Abstract: Provided are a semiconductor device and a System on Chip (SoC).

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: A hardware data compressor. A first hardware engine scans an input block of characters and uses a plurality of lists of nodes to produce back pointers to matching strings in the input block to compress the input block. Each node points to a character in the input block previously scanned and has an associated probability that a back pointer to a matching string that begins with the pointed-to character will be produced by the first hardware engine. A second hardware engine, for each list of nodes of the plurality of lists, sorts the list according to the probabilities of the nodes in the list so that higher probability nodes appear earlier in the list for use by the first hardware engine to search for matching strings during the scan of the input block of characters.

Abstract: A calibration method includes generating, by a digital-to-analog converter of a chip, a first predetermined voltage and a second predetermined voltage and outputting the same to an analog-to-digital-converter of the chip to generate a first digital code difference; determining a variation parameter according to the first digital code difference and one of a plurality of second digital code differences stored in a look up table of a memory unit of the chip; driving, by an external testing system, the digital-to-analog converter to generate the first predetermined voltage and the second predetermined voltage and output the same to the analog-to-digital-converter to generate a target code difference; and multiplying the second digital code differences with the variation parameter to calibrate a gain of the analog-to-digital converter according to the target code difference.

Abstract: Provided is a wireless communication system which has excellent communication characteristics even between antenna modules having antenna coils between which there is a large difference in outside diameter. The wireless communication system includes: a first antenna module including a first antenna coil; and a second antenna module including a second antenna coil and capable of communication by receiving a magnetic field transmitted from the first antenna module, in which the first antenna coil and the second antenna coil have mutually different outside diameters, and, out of the first antenna coil and the second antenna coil, the antenna coil having a larger outside diameter is formed in such a way that the area of an opening portion inside the innermost perimeter of an antenna pattern is not more than 120% of the outside diameter area of the other antenna coil having a smaller outside diameter.

Abstract: System and method of calibrating the DC offsets of alternate comparators in an ADC in the background based on the digital outputs of the ADC. In parallel with A/D conversion of a plurality of samples, the calibration logic uses two counters to count the occurrences of the ADC outputs that represent samples falling in a first analog range and a second analog range, respectively. The two ranges are symmetric about the MSB reference voltage and in combination cover the nominal voltage range of the bit. The DC offset is derived based on a ratio of the difference between the two counts and a sum of the two counts. The calibration logic may alternately calibrate the comparators. Each comparator may be calibrated successively based on various bits associated therewith.

Abstract: According to an embodiment, an antenna device includes a first dielectric substance and a second dielectric substance. The first dielectric substance is internally provided with a wave source. The second dielectric substance includes a first surface on which a conductor with an opening is provided, and a second surface on which a radiation element is provided, the first surface being opposed to a counter surface of the first dielectric substance, the second surface being opposed to the first surface. The first surface of the second dielectric substance is larger than the counter surface of the first dielectric substance, and a distance between the first and second dielectric substances is smaller than or equal to twice the wavelength of a used frequency.