Patents Examined by Joshua J King
  • Patent number: 7368788
    Abstract: Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: May 6, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zong-Liang Huo, Seung-Jae Baik, In-Seok Yeo, Hong-Sik Yoon, Shi-Eun Kim
  • Patent number: 7358156
    Abstract: A method of manufacturing a compound semiconductor device comprises forming a scribed groove extending from an edge of a major surface of a laminated body to an internal region on the first major surface. The laminated body has the first major surface and a second major surface and is formed by crystal growth of a compound semiconductor multilayer film on a substrate. The scribed groove is shallow at the edge and deep in the internal region. The method may further comprise separating the laminated body into first and second portions separated by a separation plane including the scribed groove by applying load to the second major surface of the laminated body.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: April 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tanaka, Masaaki Onomura, Seiji Iida, Takayuki Matsuyama
  • Patent number: 7358590
    Abstract: A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying a voltage to a pair of electrodes, the state change caused by the precipitous change in volume (such as bubble generation) is generated between the pair of electrodes. Short-circuiting between a pair of electrodes is promoted by acting force based on this state change. Concretely, a bubble generating area is provided in the memory element to generate a bubble between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: April 15, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mikio Yukawa, Yoshinobu Asami, Ryoji Nomura