Abstract: Data exchanges between an ultra-wide band communication module and a secure element are controlled such that the data exchanges pass through a near-field communication router. The near-field communication router controls routing of the data exchanges so that the data exchanges do not pass through a host circuit that is also coupled to the near-field communication router.

Abstract: The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array of memory cells. An input/output (I/O) line is shared as a data path for in-memory data switching associated with the array. An in-memory data switching network is selectably coupled to the respective shared I/O line. A controller is configured to couple to the in-memory data switching network and direct enablement of a switch protocol.

Abstract: Systems and methods are presented for secured communications in a controller area network for a vehicle system. A first electronic processor is communicatively coupled to a memory and configured to operate one or more vehicle systems. A second electronic processor is configured to generate message authentication codes to verify data communications between the first electronic processor and at least one other vehicle system controller in the controller area network. The direct memory access (DMA) module is configured to facilitate direct communications between the second electronic processor and the memory so that the first electronic processor can continue to execute other instructions while message authentication codes are generated by the second electronic processor for incoming and outgoing message data.

Abstract: To perform communication more definitely and efficiently. In order to perform communication in which a group address is used setting a plurality of arbitrary slaves to a single group and setting the group to a destination, a slave having a group-belonging capability capable of belonging to the group and performing communication is recognized. Then, in a state in which a slave having the group-belonging capability and a slave having no group-belonging capability mixedly join in a bus, the group address is assigned to the slave recognized to have the group-belonging capability. The present technology is, for example, applicable to a bus IF.

Abstract: There are provided a lighting control method, system, and device for an NVME backboard, and a medium. The method is applied to a mainboard. The method includes: executing a target code for parsing a target VPP signal upon reception of the target VPP signal, where the target code is added in the mainboard in advance and stores VPP addresses respectively corresponding to NVME backboards connected with the mainboard; parsing the target VPP signal to obtain a target VPP address corresponding to the target VPP signal; and delivering the target VPP address to a target NVME backboard corresponding to the target VPP address to light the target NVME backboard.

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.

Abstract: A bus arrangement includes a coordinator, a first subscriber, a first subscriber arrangement, and a bus. The first subscriber arrangement has a second subscriber. The bus couples the coordinator with the first subscriber and the second subscriber. The first subscriber is arranged between the coordinator and the second subscriber on the bus. The bus arrangement is configured such that the first subscriber arrangement can be decoupled from the bus in an operating phase, and such that the first subscriber cannot be decoupled from the bus in the operating phase.

Abstract: A compact expansion card riser assembly for connection of two expansion cards to horizontally oriented circuit board is disclosed. The riser assembly includes a support bracket, a first horizontal riser board, and a second horizontal riser board. The first horizontal riser board has an expansion card connector. The first horizontal riser is attached to the support bracket. The support bracket and first horizontal riser board support a horizontally oriented expansion card. The second horizontal riser board has an expansion card connector. The second horizontal riser is attached to the support bracket. The support bracket and second horizontal riser board support a horizontally oriented expansion card.

Abstract: Method and apparatus for improving continuous read operations with expanded serial interface are provided. In one aspect, a device comprises: a memory configured to store data; a buffer configured to receive data from outside of the device and transfer the received data to the memory; a plurality of input pins configured to be coupled to an expanded serial peripheral interface (xSPI); and a processor configured to: select a slave device, through the xSPI, from a plurality of slave devices, send instruction data to the slave device for data reading, receive data, through the xSPI, from the selected slave device, and receive a signal on a data strobe line of the xSPI and determine data reading operations based on the received signal.

Abstract: The present invention discloses a dual-mode USB device, which includes a USB2.0 controller, a dual-mode USB2.0 interface module and a USB interface. The dual-mode USB device alternatively works in a USB2.0 standard mode or a USB2.0 extended mode. In the USB2.0 standard mode, DP and DM signals of the USB2.0 interface are connected to a remote USB interface by DC coupling, and is compatible with remote devices using USB2.0 standard signals and protocols; in the USB2.0 extended mode, DP and DM signals of the USB2.0 interface are connected to the remote USB interface by AC coupling, which is compatible with remote devices supporting the USB2.0 extended mode.

Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Abstract: An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: A memory component can include memory cells with a memory region to store a machine learning model and input data and another memory region to store host data from a host system. The memory component can include an in-memory logic, coupled to the memory cells, to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and can provide the additional data to the other memory region or the in-memory logic based on a characteristic of the additional data.

Abstract: Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus includes a receptacle to receive a plug of a first device and a second device; a transceiver circuit coupled to the receptacle; and a controller circuit to: switch between a first mode for a first class of data transfers and a second mode for a second class of data transfers, wherein the first class preempts the second class of data transfers, schedule a data transfer with the transceiver circuit for a first endpoint of the first device at a first service interval of a bus interval when in the first mode, and schedule a data transfer with the transceiver circuit for a second, different endpoint of the second device at a second service interval that is smaller than the first service interval when in the first mode.

Abstract: Keyboard dock verification can be performed. A dock report can be created and stored on a keyboard dock as part of the manufacturing process. The dock report can include device information for the child devices of the keyboard dock. When the keyboard dock is attached to a computing device, a dock manager executing on the computing device can query the keyboard dock to retrieve device information for the keyboard dock's child devices. The dock manager can create a dock report from the retrieved device information. The dock manager can also retrieve the dock report that is stored on the keyboard dock and compare it to the dock report that the dock manager created. If the two dock reports match, the dock manager can determine that the keyboard dock is verified and can allow the keyboard dock, including its child devices, to be enumerated on the computing dock.

Abstract: Peripheral magnetic tape drives are disclosed herein. The disclosed peripheral magnetic tape drive comprises: a housing; a SAS compliant tape drive module; a power supply and a USB-C to SAS assembly. The SAS compliant tape drive module, the power supply and the USB-C to SAS assembly are disposed within the housing. The power supply module is operatively coupled to the tape drive module to supply +12V and +5V power thereto. The USB-C to SAS assembly is operatively connected to the tape drive module using a SAS data channel. The USB-C to SAS assembly is configured to enable the peripheral magnetic tape drive to interface a USB-C compliant device with the SAS compliant tape drive module. The USB-C to SAS assembly is further operatively coupled to the power supply to receive +12V power. The USB-C to SAS assembly may send and receive data using a Thunderbolt® 3 protocol.

Abstract: A circuit is provide comprising a first input coupled to a transmit data input of a bus transceiver; and a first output coupled to a bus. The circuit is configured to be coupled in parallel with the bus transceiver. The circuit is further configured to, in response to a dominant to recessive transition on the transmit data input, lower an impedance of the bus.

Abstract: A server/storage array console port for providing a service connection interface to a storage array or server is disclosed. The server/storage array console port includes a receptacle that is coupled to the server or storage array and that is configured to receive a reversible connector. The console port further includes a plurality of connection interface components integral with the receptacle. A first number of the plurality of connection interface components are for video transmission and a second number of the plurality of connection interface components are for power transmission. Video and power are transmitted simultaneously.

Abstract: According to one aspect, embodiments of the invention provide a DC-DC power converter system comprising a positive bus interface, a negative bus interface, a positive battery interface, a negative battery interface, a first converter segment coupled to the positive bus interface and the negative bus interface, a transformer coupled to the first converter segment, a second converter segment coupled to the transformer, the positive battery interface, and the negative battery interface, a bus balancer circuit coupled to the transformer, and a controller configured to identify an imbalance between a positive voltage level on a positive DC bus and a negative voltage level on a negative DC bus, and in response to identifying the imbalance, operating the bus balancer circuit to convert the first converter segment, the transformer, and the second converter segment into an inverted buck-boost converter configured to transfer energy between the positive bus interface and the negative bus interface.