Patents Examined by Julie Stein
  • Patent number: 5739069
    Abstract: An apparatus for manufacturing a semiconductor device having: a process chamber capable of being evacuated; a coil unit for generating an alternating magnetic field in the process chamber; a conductive partition unit disposed in the process chamber for defining an inner space and generating another alternating magnetic field which cancels a change in the alternating magnetic field generated in the inner space, the partition unit allowing gas to be transported between the inner space and a space outside of the inner space; a pipe for supplying process gas to the process chamber; and a pipe for exhausting gas from said process chamber. The gas supply pipe and gas exhaust pipe have a plurality of openings directed to the inner space. Radicals are efficiently generated by inductively coupled plasma, and efficiently transported by a gas flow into the inner space.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: April 14, 1998
    Assignee: Fujitsu Limited
    Inventors: Kaoru Usui, Shou Chiba
  • Patent number: 5736462
    Abstract: An intermediate layer is formed on a portion which becomes a projecting portion of a step difference formed on a semiconductor substrate, a layer to be polished having a slower polishing rate than the intermediate layer is formed to cover intermediate layer and fill a recessed portion of the step difference, and then polishing is carried out over an area from this layer to be polished to the intermediate layer. Further, it is also possible to form a stopper layer having a slower polishing rate than the layer to be polished under the intermediate layer. In the polishing, a fluctuation of the rotational torque of the polishing machine of a predetermined value or more or an interference color may be used for detection of the end point of polishing.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: April 7, 1998
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Kazuhiko Tokunaga, Shunichi Yoshigoe
  • Patent number: 5670062
    Abstract: In accordance with the invention a metal film structure having tapered sidewalls is made by the steps of applying a first layer of metal on a substrate, applying a second layer of a different material over the first layer, forming a pattern of resist on the second layer and etching the first and second layers in an etchant. The material of the second layer is chosen to interact with the metal of the first layer to increase the lateral etch rate of the second layer, thereby producing a metal film structure having tapered sidewalls. In preferred embodiments, the first layer is Cr, the material of the second layer is Mo, and the etchant is ceric ammonium nitrate. The preferred application of the method is to make conductive thin film lines for thin film transistor arrays used in active matrix liquid crystal displays.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: September 23, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Cheng-yih Lin, Paul Patrick Mulgrew