Abstract: The MOS semiconductor integrated circuit of the present invention includes: a plurality of serial transistors serially and sequentially connected to the drain of an output transistor of a current mirror circuit receiving input current; a plurality of reference voltage transistors, each connected serially between the gate of an associated one of the serial transistors and ground; PMOS transistors each supplying constant current to an associated one of the reference voltage transistors; an input transistor of an output current mirror circuit, which is connected to the drain of one of the serial transistors that is closest to the input transistor of the output current mirror circuit; and an output transistor of the output current mirror circuit for supplying output current.

Abstract: The present invention enables a pin on an integrated circuit to provide multiple duties. The internal circuit coupled to the selected pin is placed into a high impedance or sampling state based on a recurring signal so that the terminal pin can be sampled. The sampled signal is used to control the operation of the circuit, such as turning off the internal clock to place the circuit in shutdown mode. In that specific example, the integrated circuit exits shutdown mode when the sampled signal changes.

Abstract: A balance-to-single signal converting circuit of the present invention includes an anti aliasing filter (AAF) comprising an operational amplifier supplied at a non-inversion input terminal with a voltage obtained by dividing a power source voltage, for example Vdd, by resistors coupled between a power source and, for example, a ground. Each of the of the resistors may have a resistance value about twice as large as that of a resistor coupled between an inversion input terminal of the operational amplifier and the output of the operational amplifier. Accordingly, a balance-to-single signal converting circuit can be constructed without inputting to the AAF a reference voltage from a reference voltage generating circuit which is supplied to a switched capacitor filter.

Abstract: This invention relates to source-coupled logic (SCL) which is a functional derivative of emitter-coupled logic (ECL). ECL is widely recognized as having the characteristics of high speed (low propagation delay) and low power supply noise generation. The SCL of the prior art succeeds at maintaining and improving the low noise characteristics of this architecture but does not fulfill the promise of high speed that one would expect from a current-mode logic. In addition, it uses a differential form of logic that is not as flexible and easy-to-use as a reference controlled or “single-ended” logic. The SCL disclosed here has the desired high speed properties and maintains the ease of use that is a property of reference controlled ECL. In addition, the reference controlled SCL of this invention provides new capabilities that make it even more flexible than ECL in generating logical switching functions.

Abstract: The depletion-type N-channel MOS transistor regulates to lower an external power voltage, and thus generates an internal power voltage for the chip. The threshold voltage monitoring circuit detects the threshold voltage of the depletion-type N-channel MOS transistor. The differential amplifying circuit which constitutes the inverse amplifying circuit, together with resistances having the same resistance value, inverts and amplifies the threshold voltage of the depletion-type N-channel MOS transistor, detected by the threshold voltage monitoring circuit. The output voltage of the differential amplifying circuit is supplied to the gate of the deletion-type N-channel MOS transistor. The threshold voltage of the depletion-type N-channel MOS transistor is compensated with the output voltage from the differential amplifying circuit, and thus the internal power voltage is maintained at constant.

Abstract: A system and method for speed-up of the frequency switching time of a circuit, generally a voltage controlled oscillator having an operating frequency controlling input terminal. A first control circuit is coupled to the frequency controlling input terminal for maintaining the operating frequency of the oscillator at its first selected operating frequency. Circuitry is provided which is responsive to a directed change from the first operating frequency of the oscillator to a second different operating frequency of the oscillator to apply a voltage to the input terminal determined by the size of the directed change in the operating frequency and for a predetermined time period. This circuitry includes a switch coupled to the input terminal, a charge pump coupled to the switch and remote from the input terminal and a timer controlling the current output of the charge pump and the switch. The output of the charge pump is a current which is converted to a voltage.

Abstract: A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal applied to an input terminal. The first capacitor is discharged to boost a voltage at the boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an “H” level to an “L” level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal.

Abstract: The provision of a source voltage detecting circuit suitable for integrated circuits, wherein a very simple circuit arrangement makes it possible to satisfy various characteristics required by source voltage detection and to control detection voltage in wafer process. A source voltage detecting circuit, comprising a first resistor R1, a second resistor R2 and a reference voltage source RV which are connected in series between a power source VCC and the ground GND, wherein the point of connection P1 between said first and second resistors R1, and R2 is connected to the output terminal of a negative resistance characteristic section NR, and the point of connection P2 between said second resistor R2 and the reference voltage source RV is connected to the input terminal of the negative resistance characteristic section NR.

Abstract: A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor has a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.

Abstract: A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

Abstract: A circuit and a method for starting a bandgap circuit which is in a “non-start” mode. The circuit incorporates an inverter circuit with hysterysis and sharp transitions caused by a positive feedback loop. The inverter circuit, which is connected at its input to a bandgap voltage node of the bandgap circuit, activates a switching transistor when voltage (Vbg) at the bandgap voltage node is low and deactivates the switching transistor when Vbg is high. The switching transistor draws current from a critical node of the bandgap circuit, such as the drain of a current mirror PMOS transistor, when it is activated, starting the bandgap circuit.

Abstract: In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.

Abstract: A reference voltage generating circuit with MOS transistors having a floating gate is disclosed. The reference voltage generating circuit has first and second MOS transistors in which substantially the same current flows by means of a current mirror circuit. The differential voltage between the threshold voltages of the first and second MOS transistors is applied from the source of the first transistor as the reference voltage. The first and second transistors are of a construction that includes a floating gate, and the threshold voltage can be set to any value by means of the amount of charge injected to the floating gate.

Abstract: A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: Current mode charge pumps having improved power consumption characteristics and reduced peak current requirements. The current mode charge pumps utilize a differential transistor pair with a current source providing the tail current for the differential pair. The differential pair alternately steers the current of the current source through first and second fly capacitors, with additional circuitry coupling the opposite fly capacitor, previously charged, to the output of the charge pump. Selection of the tail current provides for matching of circuit performance with the required charge pump output voltage, the load current to be provided thereby and the start time requirements.

Abstract: A circuit arrangement for evaluating a binary signal defined by two current thresholds, particularly the output signal of an active sensor [(1′)], comprises a current source [(IQ′_,IQ11,IQ12,IQ13)] that can consist of individual current sources and is connected in series to the signal source, namely the sensor [(1′)]. The current source is inserted between the battery terminal [(IGW)] and the sensor terminal [(A1)] and serves simultaneously as a current limiter in case of a short circuit between the sensor terminal [(A1)] and ground [(GND)].

Abstract: A constant voltage circuit is made up of a first transistor of an N-channel type having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, a second transistor of an P-channel type having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, and a reference voltage generating circuit turning on and fixing the gate of the first transistor to the predetermined voltage when the power supply voltage is more than a predetermined voltage. Accordingly, the constant voltage circuit can apply a high voltage for the output voltage Vmcd to drains of each memory cells even if the power supply voltage Vcc is a low voltage and further can achieve the improvement of the access velocity for the data reading operation of the semiconductor memory device.

Abstract: In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are connected to a pump circuit output by means of two pass gate circuits. The transistors in each pass gate are controlled such that one pass gate circuit conducts in a first half of a clock cycle and the second pass gate circuit conducts in a second half of a clock period. Each pass gate is driven such that the full boosted signal is transferred to the output of the pump circuit and is not diminished by a threshold voltage of the pass gate circuit. The efficiency of this design keeps the output capacitor charged to a value close to the average value of boosted signal.

Abstract: A semiconductor device for outputting a reference voltage, the value of which changes depending on the ambient temperature, and a crystal oscillator device comprising the semiconductor device. The semiconductor device comprises at least one depletion MOS transistor having an overall conductivity coefficient KDO and at least one enhancement MOS transistor having an overall conductivity coefficient KEO, wherein KDO does not equal KEO and the transistors are connected in series. Thus, the semiconductor device provides an output reference voltage having a predetermined temperature characteristic which can be effectively controlled in accordance with the ambient temperature. The semiconductor device is employed in a two-level housing or in a one-level housing package so that the crystal oscillator device can have a small size and is produced easily. Also disclosed is a method of producing the crystal oscillator device.

Abstract: Capacitor voltage coefficient errors are reduced in a lossy integrator by providing oppositely oriented first and second feedback capacitors in a switched capacitor feedback circuit coupled between the output and a summing conductor connected to an inverting input of an operational amplifier. During a first clock signal, terminals of the first feedback capacitor are coupled to a reference voltage by closing first and second reset switches and the second feedback capacitor is coupled between the inverting input and the output conductor by closing first and second sampling switches. Then, during a second clock signal the terminals of the second feedback capacitor are coupled to the first reference voltage by closing third and fourth reset switches, and the second feedback capacitor is coupled between the inverting input and the output by closing third and fourth sampling switches.