Abstract: Methods, systems, and devices for techniques to improve latency for gaming applications are described. The memory system may be configured to operate in a gaming mode that may enable faster load times. In some cases, the gaming mode may enable faster game download from an external server. In some cases, the gaming mode may enable faster transferring of files between volatile storage and non-volatile storage at the memory system. The gaming mode may enable faster read and write operations, and faster switching between one or more gaming applications. The memory system may additionally or alternatively be configured to operate in a non-gaming mode which may improve reliability and retention for other, non-gaming applications. The memory system may switch between the two modes depending on an application being executed by the system.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Abstract: Methods, systems, and devices for techniques to reduce write amplification are described. A memory device may receive a write command from a host device and may determine that a quantity of commands stored in a buffer for execution by a memory array satisfies a first threshold. In some examples, the memory device may identify whether a write amplification parameter associated with the memory array satisfies a second threshold. The memory device may write data associated with the write command to the memory array using a first mode to write the data or a second mode to write the data based on determining that the quantity of commands satisfies the first threshold and/or identifying whether the write amplification parameter satisfies the second threshold. In some examples, the memory device may adjust a value of the first threshold or the second threshold or both based on the write amplification parameter.

Abstract: A computer-implemented method according to one approach includes copying data stored on a Linear Tape File System (LTFS)-based storage system to blocks of a Random Access Nonvolatile Memory (RANVM) drive. The data is copied in units of the blocks of the drive. The method further includes constructing file metadata so that the copied data on the drive is accessible as one or more files. A computer program product according to another approach includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a controller to cause the controller to perform the foregoing method. A system according to another approach includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to perform the foregoing method.

Abstract: Methods, systems, and devices for memory cell access techniques for memory systems are described. A memory system may receive, from a host system, a set of commands to write data to the memory system. The memory system may analyze a set of parameters associated with the set of commands based on receiving the set of commands. The memory system may determine whether to write the data of the set of commands to the memory system using a first mode or a second mode based on analyzing the parameters. The memory system may write the data using the first mode or the second mode based on the determining.

Abstract: Examples described herein relate to prioritizing read input/output (IO) queues in non-volatile memory express (NVME) storage devices. An NVME controller includes a host port, which may be associated with a host and communicate with NVME storage devices. A utilization time of the host port is determined. In response to determining that the utilization time of the host port is below a host port utilization threshold, the NVME controller may create a candidate list of NVME storage devices based on utilizations, throughputs, busy time periods, and IO request completions of the NVME storage devices. For each NVME storage device included in the candidate list, a number of read requests in a read IO queue at the NVME storage device may be determined. A priority rank may be assigned to the read IO queue at each NVME storage device based on the number of read requests in that read IO queue.

Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

Abstract: The present disclosure generally relates to a non-volatile memory express (NVMe) dual port controller occupying less real estate on an application specific integrated circuit (ASIC). Rather than utilizing separate NVMe modules in the controller, with each module dedicated to a single port, the dual ports can share the same module. The host device believes that there are dedicated module resources because the module has two NVMe registers to provide the host device with the feeling that there are dedicated modules. Additionally, an interconnect between the ports and the registers contributes to providing the host device the feeling that there are dedicated modules. Furthermore, the rather than losing the capabilities of a second module when operating in single port mode, all of the capabilities of the only module are available when operating in either single port mode or dual port mode.

Abstract: A system for controlling processor operations is disclosed that includes a first function configured to be performed by one or more algorithms operating on a processor to identify one or more participating storage controllers, each having a software controller handle, and to cache the software controller handles during a query to a driver. A second function configured to be performed by one or more algorithms operating on the processor to invoke the driver with the cached software controller handles.

Abstract: Embodiments of the present disclosure relate to establishing persistent cache memory as a write tier. An input/output (IO) workload of a storage array can be analyzed. One or more write data portions of the IO workload can be stored in a persistent memory region of one or more disks of the storage array.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module includes a plurality of planes, and each plane includes a plurality of blocks; and the control method includes the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

Abstract: A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising: providing a multi-processor having a plurality of processing units; receiving a trim command and a logical block address (LBA) range sent from the host device; separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range; using the processing units to execute the N threads individually; and maximizing a number of execution cycles during which the processing units are busy.

Abstract: Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.

Abstract: Methods, systems, and devices for address verification for a memory device are described. When a memory device receives a write command, the memory device may store, in association with the data written, an indication of a write address associated with the write command. When the memory device receives a read command, the memory device may retrieve data and a previously stored write address associated with the retrieved data, and the memory device may verify a read address associated with the read command against the previously stored write address associated with retrieved data. Thus, for example, the memory device may verify whether data read from the memory array based on an address associated with a read command is data that, when previously written to the memory array, was written in response to a write command associated with a matching address.

Abstract: A memory component includes a memory region to store a machine learning model and input data and another memory region to store host data from a host system. A controller can be coupled to the memory component and can include in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and a decoder can receive the additional data from the bus and can transmit the additional data to the other memory region or the in-memory logic of the controller based on a characteristic of the additional data.

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.

Abstract: A sensing system includes a patient interface module (PIM) communicatively disposed between a processing system and a sensing device configured to obtain measurement data associated with a body of a patient while positioned within the body, the sensing device comprising a memory, wherein the patient interface module comprises: a controller operable to: read data stored on the memory of the sensing device using a first signal voltage; and write to the memory to disable further operation of the sensing device using a second signal voltage; and a voltage switch configured to selectively output the first signal voltage or the second signal voltage.