Abstract: A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.

Abstract: Some examples described relate to securing a memory device of a computing system. For instance, a method may comprise comparing a command for the memory device to each command in a list of commands. The command is accepted when the command matches an authorized command in the list of commands. The accepted command is issued to the memory device.

Abstract: Managing direct memory access (DMA) by: defining a translate control entity (TCE) cache flag for cache memory addresses, receiving a DMA TCE related request, checking the TCE cache flag status, and completing the TCE related request according to the TCE cache flag status.

Abstract: Provided is a storage system and a data management method of a storage system enabling system-wide data deduplication. The storage system has a plurality of storage apparatuses in which one or a plurality of logical volumes are provided. Based on data information of data obtained through the generation of a request to write to a logical volume in the storage system, one storage apparatus among the plurality of storage apparatuses calculates, for a plurality of combinations of storage apparatus and logical volume in the storage system, a data capacity when duplicate data is removed for each of the storage apparatuses, calculates the total of the calculated data capacities as the total capacity of the whole storage system, and performs optimal arrangement arithmetic processing to output information indicating a combination with the smallest total capacity among the plurality of combinations.

Abstract: A method for managing objects stored in memory is presented. The method may include receiving, by a memory allocator in a garbage collected system, a first free memory chunk. The method may include creating a node to associate with the first free memory chunk and ensuring that a first memory region containing the node will be considered to be free memory during a sweeping phase of the garbage collected system.

Abstract: A solid state drive system and method receives read commands, write commands, and/or file system updates. The solid state drive system then determines the latency estimate for performing each of those commands asynchronously. The solid state drive system may utilize internal processes to determine the latency estimate. The latency estimate may include random access latency, block erase time, outstanding workload latency, garbage collection time, metadata write time, etc. The latency estimate is then returned to the host device. The host device may utilize the latency estimate to workload balance solid state drive systems.

Abstract: An LL server (LLS) may process metadata requests for a file system in LL mode in a distributed file storage services (DFSS). For requests that require allocating blocks to file system objects in the backing store, instead of relying on distributed transactions used for file systems in high throughput (HT) mode, a pool of blocks may be pre-allocated for the LL file system in the backing store, and a free block list may be maintained in local memory of the LLS. When a metadata operation requires blocks to be allocated, the blocks are assigned to the respective object from the blocks in the pool. A background process may allocate new blocks in the pool upon the number of blocks dropping below a threshold, or upon block allocation rate for the file system increasing.

Abstract: A storage device includes a plurality of flash memories, a first local controller connected to a first group of flash memories among the plurality of flash memories, a second local controller connected to a second group of flash memories among the plurality of flash memories, and a global controller. The global controller transmits commands to the first local controller and the second local controller. The first local controller includes a first processor that transmits first information on a type and number of commands associated with an operation performed on the first group of flash memories to the global controller. The second local controller includes a second processor that transmits second information on a type and number of commands associated with an operation performed on the second group of flash memories to the global controller.

Abstract: A processing device is configured to receive a plurality of input-output requests in a storage system, the input-output requests comprising read requests and write requests, to determine priorities of respective ones of the read requests, to place one or more of the read requests each having a relatively low priority in a first one of a plurality of queues in one of a plurality of processing cores of the storage system, to place one or more of the read requests each having a relatively high priority in a second one of the plurality of queues in the processing core, and to place the write requests in the first queue. The storage system services the read requests and the write requests from their corresponding ones of the first and second queues, illustratively resulting in reduced read latency for one or more relatively high priority read requests placed in the second queue.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a flash memory to store data and support for a number of device streams. The SSD may also include an SSD controller to manage reading data from and writing data to the flash memory. The SSD may also include a host interface logic, which may include a receiver to receive the commands associated with software streams from a host, a timer to time a window, a statistics collector to determine values for at least one criterion for the software streams from the commands, a ranker to rank the software streams according to the values, and a mapper to establish a mapping between the software streams and device streams.

Abstract: An access request processing apparatus comprises, a processor determines an object cache page according to a write request when receiving the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.

Abstract: Provided are techniques for handling cache and Non-Volatile Storage (NVS) out of sync writes. At an end of a write for a cache track of a cache node, a cache node uses cache write statistics for the cache track of the cache node and Non-Volatile Storage (NVS) write statistics for a corresponding NVS track of an NVS node to determine that writes to the cache track and to the corresponding NVS track are out of sync. The cache node sets an out of sync indicator in a cache data control block for the cache track. The cache node sends a message to the NVS node to set an out of sync indicator in an NVS data control block for the corresponding NVS track. The cache node sets the cache track as pinned non-retryable due to the write being out of sync and reports possible data loss to error logs.

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.

Abstract: A first memory request including a first virtual address is received. An entry in memory is accessed. The entry is selected using information associated with the first memory request, and includes at least a portion of a second virtual address (first data) and at least a portion of a third virtual address (second data). The difference between the first data and the second data is compared with differences between a corresponding portion of the first virtual address and the first data and the second data respectively. When a result of the comparison is true, then a fourth virtual address is determined by adding the difference between the first data and the second data to the first virtual address, and then data at the fourth virtual address is prefetched into the cache.

Abstract: Described examples include a system having a non-volatile memory including a binary section, a first page table and a second page table. The system also has a volatile memory and a processor coupled to the non-volatile memory and the volatile memory, the processor operable to use the first page table when the processor is initialized, the first page table including a first pointer to the binary section, the processor operable to cause copying of the binary section of the non-volatile memory to the volatile memory to create a copied binary section in the volatile memory, and the processor operable to use the second page table when the copying is complete, the second page table including a second pointer to the copied binary section.

Abstract: In a coprocessor performing data processing by supplementing functions of a CPU of a host or independently of the CPU, a processing element corresponding to a core of the coprocessor executes a kernel transferred from the host, and a server manages a memory request generated according to an execution of the kernel by the processing element. A memory controller connected to the resistance switching memory module moves data corresponding to the memory request between the resistance switching memory module and the processing element in accordance with the memory request transferred from the server. A network integrates the processing element, the server, and the memory controller.

Abstract: A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Abstract: A storage system in one embodiment comprises a plurality of storage devices and a storage controller. The storage system is configured to participate as a target storage system in a replication process with a source storage system. In conjunction with the replication process, the target storage system is configured to receive from the source storage system replication data for at least one storage volume subject to replication from the source storage system to the target storage system, to generate a first snapshot for the storage volume, to monitor additional replication data received from the source storage system for the storage volume after generation of the first snapshot, and responsive to the monitored additional replication data satisfying one or more specified conditions, to perform at least one of the following operations: (i) generating a subsequent snapshot for the storage volume; and (ii) marking the first snapshot with a priority indicator.

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.