Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

Abstract: Described herein is a technique capable of improving the controllability of firm thickness distribution. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber; a first and a second gas supply system; an exhaust system; and a controller for controlling the first and the second gas supply system and the exhaust system to form a film. The first gas supply system includes: a first and a second storage part; a first gas supply port for supplying a gas stored in the first storage part from an outer periphery toward a center of a substrate; and a second gas supply for supplying the gas stored in the second storage part from the outer periphery along a direction more inclined toward the outer periphery than a direction from the outer periphery toward the center of the substrate.

Abstract: Disclosed herein are methods for manufacturing an integrated circuit (IC) structure, e.g., for manufacturing a metallization stack portion of an IC structure, with one or more self-aligned vias integrated in the back end of line (BEOL), and related semiconductor devices. The methods may employ direct metal etch for scaling the BEOL pitches of the metallization layers. In one aspect, an example method results in fabrication of a via that is self-aligned to both a metal line above it and a metal line below it. Methods described herein may provide improvements in terms of one or more of reducing the misalignment between vias and electrically conductive structures connected thereto, reducing the RC delays, and increasing reliability if the final IC structures.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: A semiconductor device according to an embodiment includes a stacked body including a plurality of conductive layers and a plurality of first insulation layers alternately stacked in a first direction. The conductive layers each include a first metal layer and a second metal layer. The first metal layer contains a first metal element and a substance that is chemically reactive with a material gas containing the first metal element. The second metal layer contains the first metal element and has a lower content of the substance than the first metal layer. The first metal layer is disposed between the first insulation layers and the second metal layer.

Abstract: A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises an upper portion having a first width, and a lower portion vertically interposed between the upper portion and the contact structures. The lower portion has a tapered profile defining additional widths varying from a second width less than the first width at an uppermost boundary of the lower portion to a third width less than the second width at a lowermost boundary of the lower portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: A contact resistance monitoring device, a manufacturing method thereof, and a display panel are provided. The contact resistance monitoring device includes a substrate, a gate metal layer disposed on the substrate, an interlayer dielectric layer disposed on the substrate, a source and drain metal layers disposed in the recessed hole of the interlayer dielectric layer, and a pixel electrode layer disposed on the interlayer dielectric layer and the source and drain metal layer.

Abstract: A method includes etching a substrate to form a semiconductor fin, forming a gate stack on a top surface and sidewalls of the semiconductor fin, and forming a first recess in the semiconductor fin on a side of the gate stack, wherein forming the first recess comprises, performing a first etching process to form a first portion of the first recess, depositing a first dielectric layer on sidewalls of the gate stack and the first portion of the first recess, performing a second etching process to form a second portion of the first recess using the first dielectric layer as a mask, wherein the second portion of the first recess extends under the gate stack, and performing a third etching process to remove the first dielectric layer.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

Abstract: A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

Abstract: An operation method and an electronic device are provided. A phone call is established while a display of the electronic device is activated. A proximity sensor of the electronic device is turned on. A supply of power to the proximity sensor is controlled to emit light through a plurality of pixels in a portion of the display corresponding to a position of the proximity sensor and the light emitted by the proximity sensor and reflected by an object is received to identify a distance between the electronic device and the object, if the plurality of the pixels in the position corresponding to the proximity sensor are deactivated during the phone call. The supply of power to the proximity sensor is blocked if the plurality of pixels in the portion of the display corresponding to the proximity sensor are activated during the phone call.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first P-type metal oxide semiconductor field effect transistor (p-MOSFET) having a first fin extending along a first direction and comprising a first semiconductor layer, wherein the first fin comprises a first recess formed in a top of the first fin, the first recess having a bottom surface and a sidewall surface extending upwardly from the bottom surface. The semiconductor device structure also includes a first gate structure disposed in the first recess and in contact with the bottom surface and the sidewall surface, the first gate structure extending along a second direction substantially perpendicular to the first direction. The semiconductor device structure further includes a first spacer disposed on opposite sidewalls of the first gate structure and in contact with the first fin and the first gate structure.

Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.

Abstract: A method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source/drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. A metal plug is then formed over the portion of the exposed source/drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.

Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.

Abstract: A preparation method for a metal oxide nanoparticle film and an electrical component, comprising: preparing a halogen ligand-containing metal oxide nanoparticle by performing heated alcoholysis of a metal halide in an organic alcohol; and employing a solution method on the halogen ligand-containing metal oxide nanoparticle to prepare a halogen ligand-containing metal oxide nanoparticle film. The halogen ligand-containing metal oxide nanoparticle is produced by means of performing the alcoholysis of the metal halide, then the halogen ligand-containing metal oxide nanoparticle is prepared into the film, and then a halogen is utilized once again in a passivation processing of the film, this not only further reduces defects on the surface of the metal oxide nanoparticle, but also further improves charge transfer between the metal oxide nanoparticle and an active functional layer and increases transfer efficiency, thus increasing component efficiency.