Abstract: A method of counting red blood cells suspended in a blood sample is disclosed which can judge the presence or absence of clogging in the sample passage system of a blood cell counting apparatus. In this method, for example, the counting of red blood cells for a period of 200 msec is repeated 50 times, the means value X and standard deviation SD of 50 red blood cell counts each indicating the number of red blood cells per unit time (equal to 200 msec) are calculated, and when one of the red blood cell counts deviates from the mean value X by more than 3SD, such deviation is judged to presage clogging in the sample passage system. Further, each of the red blood cell counts can be displayed on the fluorescent screen of a CRT display.

Abstract: A method and means for improving the frequency resolution in a digital oscillator is described. According to the principles of the present invention, a digital oscillator may be comprised of a frequency latch, a phase accumulator, and a ROM based waveform generator. Improved frequency resolution is achieved in the digital oscillator, without increasing ROM size by quantizing the summed output of a dither generator and the phase accumulator before sending the resultant multi-bit signal to a ROM. The contents of the ROM are sequentially addressed with the resultant multi-bit signal. The output of the ROMs comprise digital words corresponding to a desired waveform envelope.

Abstract: Method of counting particles of seed, fertilizer, and other materials employed in agriculture acoustically. The particles to be counted are conveyed against an impact plate in such a way as to start it oscillating, generating electric signals that are processed to determine the number of particles. In order to count the exact number of individual particles passing a test point with relatively high precision and by acoustical means, at least one definite oscillation amplitude that is characteristic of the impact of one particle is determined and stored and a comparable actual oscillation amplitude is determined as the particles strike against the impact plate, is compared with the stored oscillation amplitude, and, if it is shorter than the characteristic amplitude, one particle counted, or, if it is higher than the characteristic amplitude, the inference made that another particle has struck the plate.

Abstract: A variable-ratio frequency divider has a D flip-flop which makes possible high-speed operation, and the number of frequency divisions is made variable by changing the transmission delay time of a delay element included in a feedback loop from the output Q to a predetermined terminal of the D flip-flop.

Abstract: An electronic phase shifter utilizes a serrodynable digital phase shifter which is driven by the output of a multi-bit counter. The counter in turn has its clock input driven by a pulse train which produces the desired frequency translation for noise and deception jamming. Alternatively, the counter has jam inputs for electronic antenna steering and electronic phase shift applications. In order to compensate for step phase error which causes undesirable spurious sidebands, the cells of the phase shifter are pretested for individual phase errors and an interface memory is provided which by use of a corrected counter code minimizes the errors.

Abstract: An electronic pedometer for use on a footwear is disclosed. The pedometer comprises a step sensor carried by the footwear for sensing each step that the user takes to provide an output indicative thereof. Connected to the sensor is a mount base which is secured to the footwear and has thereon a first terminal electrically connected to the step sensor. A counter, which is detachably mounted on the mount base, has therein various electronic components forming a computing circuit and includes a display section. The counter is provided with a second terminal which comes into electrical connection with the first terminal on the mount base when mounted thereon so that the computing circuit receives the outputs from the sensor to compute based thereupon the number of steps taken and the distance travelled by the user. The resulting measurements of the computing circuit are visually indicated on the display section of the counter.

Abstract: A pulse counting device wherein a number of pulses is stored in a first register out of a plurality of registers, and subsequently a new pulse number counted is stored in the first register and pulse numbers stored in the registers are successively shifted with a pulse number erased from a final register. The pulse numbers stored in the respective registers are corrected dependent on the latest pulse number stored in the first register, and a value dependent on the corrected values stored in all of the registers is displayed. If the latest pulse number is abruptly varied in excess of a certain preset value upon comparison with the pulse numbers in the registers, then the pulse numbers in the registers are corrected with a value dependent on the latest pulse number.

Abstract: A register circuit for serial transmission or reception of digital data in a microprocessor controlled system is provided. A first plurality of rank ordered latches is provided to receive in parallel data to be transmitted. A second plurality of rank ordered latches is provided wherein each of the second plurality of latches except the highest ranked latch interconnects the first plurality of latches. The first and second plurality of latches function together to serially clock output data to be transmitted. The two pluralities of latches form a single register circuit which also serially receives data and latches the received data in response to a control circuit implemented as a "walking one" register. After the serially received data is latched, the data is provided for use by the microprocessor controlled system in parallel output form.

Abstract: An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.

Abstract: A twisted ring counter has a NOR gate with inputs from outputs of the last two stages thereof to detect and be activated by a combination of outputs which is found in all modes of operation of the counter. When activated by the combination, the gate provides an output to reset the counter to an all-ZEROs condition.

Abstract: A wide band analog frequency divider circuit operable at a high frequency in the GHz band. The analog frequency divider circuit comprises an LC series circuit having a capacitor and an inductor connected between the anode and the cathode of a diode, and means for applying a forward bias to the diode. The input signal is supplied from the anode side of the diode, and the output is delivered from the cathode side, or the anode side if the cathode is grounded.

Abstract: In the particular embodiment of the invention described in the specification, a variable resistor is connected in potentiometer fashion to a DC power source and a time interval is selected according to the position of the movable contact. The ratio of the partial voltage provided by the movable contact to the full voltage applied to the resistor is determined and an oscillator signal target count for the selected time interval is computed from a count corresponding to the total voltage. The arrangement permits accurate time interval determination which is independent of variations in the supply voltage, variations in resistance value of the variable resistor, or environmental changes.

Abstract: A velocity detection apparatus for elevators wherein the time interval between movement magnitude pulses produced at a frequency-representing velocity of the cage of an elevator is detected, and the fixed frequency of sampling pulses is modulated using a modulation coefficient determined by the ratio of the fixed frequency of the sampling pulses to the frequency of the movement magnitude pulses so as to obtain a modulated pulse signal during the interval between the movement magnitude pulses from which the velocity of the elevator cage is obtained. Provision is made to include two memory units for storing the latest two count values on the basis of a sampling pulse signal to determine the difference therebetween corresponding to the velocity of the elevator cage. In an alternate embodiment, a pair of counters is provided for counting both the modulated pulses and the movement magnitude pulses of the elevator to produce count values representing the velocity of the elevator.

Abstract: A digital clock generator circuit which accepts a rate signal and a master clock signal and generates an output clock signal exhibiting a frequency which is programmed by the rate signal is disclosed. A constant duty cycle characteristic of the output clock signal is obtained regardless of the output clock signal's frequency. A memory element which generates the output signal is placed in one logical state when a counter portion of the present invention reaches a terminal count. The memory element is placed in an opposing logical state whenever the counter achieves 1/2 of its programmed value. A duty cycle compensator makes small timing adjustments to compensate for any truncation error which occurs in dividing the rate signal by two.

Abstract: This circuit provides a digital output indicating the presence or absence of the infrared (IR) carrier signal. The incoming IR signal is sampled by a clock at a frequency which is about 4 times the carrier frequency. The high and low samples are tabulated in two counters in a race. When 8 high or 16 low samples are counted, the envelope status flip flop is set or reset, respectively, and both counters are reset. The output of the envelope status flip flop represents the envelope of the IR carrier signal.

Abstract: An input circuit for a charge transfer device in which within a region of the input gate of its charge transfer element the potential barrier same as that in the transfer section thereof is provided and the same digital input signal is supplied to a pair of input gates.

Abstract: A binary synchronous bit-sliced counter comprising a plurality of cascaded identical stages (slices). Each stage only requires for its operation a source of potential V.sub.dd, a carry-in signal input line, a clock signal input line, a reset signal input line and a carry-out signal output line. Cascading of the slices is implemented by connecting the carry-out signal output line of one slice to the carry-in signal input line of another slice and connecting the clock signal and reset signal input lines to all cascaded stages in parallel.

Abstract: The invention is concerned with a digital ratemeter comprising a count difference circuit for adding input pulse signals and subtracting the frequency of the divider pulse, an integrator for integrating positive or negative count values from the count difference circuit, a feedback unit for receiving an integral count value from the integrator as input, thus generating a divider pulse frequency, and performing exponential transformation of the divider pulse frequency, whereby the integral count value is a count rate output and a fixed measurement accuracy in the overall range is attained.

Abstract: An adjustable time delay circuit 10, 50 includes a time delay line 12 including a plurality of series connected time delay units 18a-p. During adjustment, sampled signals along the delay line 12 are compared with a reference signal by NOR-gates 22e-m. Upon a comparison being attained, the output of the corresponding NOR-gate 22e-m sets a selected flip-flop 30e-m which in turn routes the signal at a selected delay line tap 38e-m through a NOR-gate 34e-m to an output OR-gate 40. The tap 38e-m selected, compensates for component propagation characteristics thus maintaining a predetermined time delay through the time delay circuit 10.

Abstract: A Geiger-Mueller tube-based radiation measurement device includes circuitry for the correction of the dead time losses associated with the Geiger-Mueller tube. As the event count rate rises, the transfer function (e.g., the closed loop voltage gain) of an operational amplifier responding to an event count rate signal is modified to compensate for dead time losses experienced at high count rates. Preferably, an analog switch controlled by the event count rate signal automatically sets the voltage gain of the operational amplifier at a level corresponding to the desired amount of dead time compensation required to provide an accurate measurement of actual events. The dead time correction circuitry disclosed herein finds practical application in the use of well-known analog rate meter circuits of the charge pump type.