Patents Examined by Kenneth A Gross
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Patent number: 6708333Abstract: A computer-implemented method and system for reporting failures in an application program module to a corporate file server. The failure may be a crash or a set-up failure. Once detected, the program failures are categorized, i.e. bucketed, and reported directly to a local file server operated by a corporation. The corporate file server may be used to store the failures encountered by users in a corporate environment until these failures are reported to a server operated by the manufacturer of the program module (a destination server). Once the failures are reported to the destination server, developers or programmers may examine the data and determine what is causing the failures in the program module. A failure reporting executable on the user's computer provides communications between the failed application program module and the local file server.Type: GrantFiled: June 23, 2000Date of Patent: March 16, 2004Assignee: Microsoft CorporationInventors: Kirk A. Glerum, Matthew J. Ruhlen
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Patent number: 6665865Abstract: Synchronization optimization for statically compiled Java programs is performed in three phases: Thread closure analysis, Alias analysis, and Specialization and transformation. Thread closure analysis bounds the number of thread instances constructed at each thread allocation site, and determines the set of methods potentially executed by each thread instance. Alias analysis generates equivalence class representation based alias signatures for each method. These signatures describe the aliasing and synchronization behavior of each method. The specialization and transformation phase traverses a call graph in a top-down manner starting from the program entry point, and creates specialized copies of methods when they can be individually optimized. A synchronization operation is removed from the code whenever it can be proven that all objects reaching the operation at runtime can be synchronized by at most one thread instance.Type: GrantFiled: April 27, 2000Date of Patent: December 16, 2003Assignee: Microsoft CorporationInventor: Erik Ruf
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Patent number: 6637024Abstract: A method find computer program product for debugging a virtual machine, preferably a target lava virtual machine, without need for the virtual machine to comprise debug information required by a debugger, the method being applied during communication of request packets between the debugger and the virtual machine during execution of the debugger, the method comprising the steps of receiving the request packets from the debugger prior to communication of the request packets to the virtual machine, processing the request packets whereby the required debug information is provided to predetermined packets thereof, transmitting the processed request packets for communication to the virtual machine, receiving reply packets from the virtual machine, processing the reply packets for reply to the debugger, and transmitting the processed reply packets to the debugger.Type: GrantFiled: May 3, 2000Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Graeme D. Johnson, Marcio Q. Marchini
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Patent number: 6637019Abstract: Software modeling of hardware components is conducted by partitioning the software into components or parts that are comparable to the components of the hardware. The parts are then configured through the use of plugs and connectors to replicate the hardware. The plugs are either import, export, splitter or compound plugs. The connectors ensure that the parts are capable of interfacing with one another in a communicative manner.Type: GrantFiled: April 10, 2000Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventor: Mark Anthony Rinaldi
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Patent number: 6591415Abstract: A method and system for producing multiple copies of an executable software object, in which a copy is functionally identical to all other copies while being structurally unique, alter the source code according to parameters specified by a seed and a set of preferences. High-level source code is translated to assembly code. Selected procedures from the assembly code are blended to form larger procedures functionally equivalent to the original procedures. Instructions within procedures are reshuffled, while the original flow of execution is conserved. Dummy opcodes are interspersed with executable instructions. The resulting modified code is translated to object code and an executable object is constructed. The invention is also embodied as a computer readable program product on a computer readable medium. Each copy bears a unique fingerprint that allows the producer of the product to exercise control over the use of the software product and prevent unauthorized use and copying.Type: GrantFiled: April 25, 2000Date of Patent: July 8, 2003Assignee: Trymedia SystemsInventor: Andres Torrubia-Saez
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Patent number: 6588008Abstract: A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.Type: GrantFiled: April 11, 2000Date of Patent: July 1, 2003Assignee: International Business Machines CorporationInventors: Marco C. Heddes, Ross Boyd Leavens, Mark Anthony Rinaldi
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Patent number: 6564373Abstract: On completion of execution of a current block of instructions, a block completion process searches for potential successor blocks, using block descriptors and egress data structures. For each potential successor block, the process compares a set of entry conditions associated with the block with the exit conditions of the current block and, if a match is found, selects the potential successor block as the current block and executes it. A consistency check is performed, to compare the block identity of the successor block with an expected block identity. Block-following code is selectively planted into translated blocks, to call a successor block directly, by-passing the block completion process. The block-following code is optimised, in that it contains tests for entry conditions only if the results of those tests are not known at the time the block-following code is planted.Type: GrantFiled: March 10, 2000Date of Patent: May 13, 2003Assignee: International Computers LimitedInventors: Kevin Hughes, Martin Pixton