Abstract: Provided are an array substrate, a display panel, a display apparatus and a preparation method therefor. The array substrate comprises: a base substrate; and multiple pixel units arranged on one side of the base substrate, each of the pixel units comprising: a thin-film transistor and an electroluminescent structure, and a shading structure located between the thin-film transistor and the base substrate, wherein the thin-film transistor comprises: an active layer located on one side, away from the base substrate, of the shading structure; the electroluminescent structure comprises: first electrodes for driving the pixel units; and one of the shading structure and the active layer is a same-layer structure fabricated by the same mask plate as the first electrodes so as to reduce the number of mask procedures required in preparation of an array substrate.

Abstract: An organic light-emitting display panel and a fabrication method thereof are provided. The organic light-emitting display panel comprises a substrate; an organic light-emitting device disposed on a side of the substrate, wherein the organic light-emitting device has a first side facing the substrate and an opposing side; and an encapsulation layer disposed on the opposing side of the organic light-emitting device. The encapsulation layer includes at least one organic encapsulation layer, and the at least organic encapsulating layer has a polymer network of cross-linked polyorganosiloxane.

Abstract: The disclosure relates to a dual-interface integrated circuit (IC) card module for use in a dual-interface IC card. Embodiments disclosed include a dual-interface integrated circuit card module (150), the module comprising: a substrate (104) having first and second opposing surfaces; a contact pad (102) on the first surface of the substrate; an integrated circuit (110) on the second surface of the substrate (104), the integrated circuit (110) having electrical connections to the contact pad (102) through the substrate (104); and a pair of antenna pads (108) disposed in recesses (103) in the second surface of the substrate (104) and electrically connected to corresponding antenna connections on the integrated circuit (110).

Abstract: A solid-state storage device includes a housing, a wiring board and a semiconductor package unit. The housing is formed with a heat-dissipating recess thereon. The wiring board is fixed in the housing. One side of the semiconductor package unit is mounted on the wiring board, and the other side of the semiconductor package unit is embedded in the heat-dissipating recess. A top surface and lateral surfaces surrounding the top surface of the semiconductor package unit are all thermally connected to the housing in the heat-dissipating recess.

Abstract: A trench is formed through a plurality of layers that are disposed over a first substrate. A first deposition process is performed to at least partially fill the trench with a first dielectric layer. The first dielectric layer delivers a tensile stress. A second deposition process is performed to form a second dielectric layer over the first dielectric layer. A third deposition process is performed to form a third dielectric layer over the second dielectric layer. The third dielectric layer delivers a first compressive stress.

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed outside of the display area. The display area includes a plurality of pixels. The display device further includes an inorganic insulating layer disposed in the display area. The inorganic insulating layer includes a groove disposed in a region between the plurality of pixels. The display device further includes an organic material layer filling the groove, a first connection wiring, and a second connection wiring. The first connection wiring is disposed on the organic material layer, overlaps the plurality of pixels, and extends in a second direction. The second connection wiring is insulated from the first connection wiring, and extends in a first direction that crosses the second direction.

Abstract: An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.

Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.

Abstract: Disclosed is a semiconductor radiation detector assembly including a detector chip having a front side for receiving radiation and a back side; and a flexible substrate including a center portion having its front side attached to the back side of the detector chip and a plurality of strips extending from the center portion and bent to protrude away from the detector chip, wherein the flexible substrate includes a plurality of conductive tracks that extend on a surface of the strips from the center portion towards lateral ends of the strips for electrical coupling and mechanical attachment to one of a plurality of contact pins, and wherein the detector chip is electrically coupled to at least one of the conductive tracks.

Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.

Abstract: A method includes providing a substrate; forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench; forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench; depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches; recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; and forming a gate electrode layer over the gate dielectric layer in the first and second gate trenches.

Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.

Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.

Abstract: Provided is a three dimensional integrated circuit (3DIC) structure including a first die, a second die, and a hybrid bonding structure bonding the first die and the second die. The hybrid bonding structure includes a first bonding structure and a second bonding structure. The first bonding structure includes a first bonding dielectric layer and a first bonding metal layer. The first bonding metal layer is disposed in the first bonding dielectric layer. The first bonding metal layer includes a first via plug and a first metal feature disposed over the first via plug, wherein a height of the first metal feature is greater than or equal to a height of the first via plug. A method of fabricating the 3DIC structure is also provided.

Abstract: An IGBT module includes a heat dissipation base plate. A first ceramic heat dissipation element is embedded in the heat dissipation base plate. A first wiring layer is provided on the surface of the heat dissipation base plate. The first side of an IGBT chip is mounted onto the first wiring layer. The second side of the IGBT chip is provided with a heat conductive metal plate. A first heat dissipation plate having a first through hole is provided on a side of the first wiring layer. The IGBT chip and the heat conductive metal plate are located in the first through hole. A second wiring layer is provided on a side of the first heat dissipation plate away from the IGBT chip. The second wiring layer is provided on a side of the heat conductive metal plate.

Abstract: Disclosed herein is a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a stack of sacrificial layers on a substrate. A U-shaped trench is formed in the stack of the sacrificial layers. A first U-shaped channel layer is deposited in the U-shaped trench. A first U-shaped sacrificial layer is conformally formed covering the U-shaped channel layer. A second U-shaped channel layer is conformally deposited covering the first U-shaped sacrificial layer. A gate is formed around the first and the second U-shaped channel layers.