Abstract: Proposed are a storage system and its control method capable of dealing with the unique problems that arise when using a nonvolatile memory as the memory device while effectively preventing performance deterioration. This storage system is provided with a plurality of memory modules having one or more nonvolatile memory chips, and a controller for controlling the reading and writing of data from and in each memory module. The memory module decides the nonvolatile memory chip to become a copy destination of data stored in the nonvolatile memory when a failure occurs in the nonvolatile memory chip of a self memory module, and copies the data stored in the failed nonvolatile memory chip to the nonvolatile memory chip decided as the copy destination.

Abstract: A laundry machine includes a drum supported at least two spaced apart support locations for rotation about a rotation axis. A balance correction system is able to apply a variable amount of a balance correction mass at a selectable angular location of the drum at least two spaced apart locations along the drum rotation axis. A controller receives outputs of a set of sensors, and is programmed to continuously calculate balance corrections to apply.

Abstract: Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss in response to determining the page address miss in a page addressing buffer, and saving the mapping as an entry in an array. The computer implemented method creates a preserved array from the array in response to determining the dispatched partition to be an undispatched partition. The computer implemented method further analyzes of the preserved array for a compressed page in response to determining the undispatched partition is now redispatched, and decompresses the compressed page prior to the partition being redispatched.

Abstract: A computer-implemented method for creating reference-based synthetic backups. The method may include identifying a first set of references that identify data of a first backup. The first backup may represent at least a portion of a data set at a first time. The method may also include identifying a second set of references that identify data of a second backup. The second backup may represent changes made to the data set between the first time and a second time. The method may further include creating a synthetic backup that represents at least a portion of the data set at the second time by aggregating one or more references from the first set of references and one or more references from the second set of references. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.

Abstract: A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

Abstract: A method and an apparatus for selecting one or more applications running in a data processing system to reduce memory usage according to information received from the applications are described. Notifications specifying the information including application specific memory management capabilities may be received from the applications. A status of memory usage indicating lack of available memory may be determined to notify the selected applications. Accordingly, the notified applications may perform operations for application specific memory management to increase available memory.

Abstract: A generation-code storage unit stores therein a generation code in association with identification information for identifying the block datum. A generation-code managing unit assigns a new generation code to a detected consecutive data set and any block datum included in writing data other than the consecutive data set and stores the assigned generation code in the generation-code storage unit. A data writing unit adds the new generation code to the block datum or consecutive data set included in the writing data and writes it to a storage unit. A determining unit determines whether the generation code added to a read block datum or consecutive data set is accordant with the generation code of the read block datum or consecutive data set stored in the generation-code storage unit. A data transmitting unit transmits, when the generation codes are accordant, the read block datum or consecutive data set.

Abstract: The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory channel is disclosed that includes multiple memory units, with each memory unit comprising multiple garbage collection units. The memory channel also includes a controller that is communicatively coupled to the multiple memory units. The controller selects a memory unit of the multiple memory units for garbage collection based on a calculated number of memory units, of the multiple memory units, to garbage collect.

Abstract: A computing system includes computer memory of a number of different memory types. An application program compiled for execution on the computing system controls access to a field of a record in the computer memory of the computing system by defining a record that includes one or more fields, the one or more fields including a restricted field having a specification of restricted accessibility when the restricted field is allocated in a particular memory type; allocating an instance of the record in memory of the particular memory type; and denying each attempted access of the restricted field while the record is allocated in the particular memory type.

Abstract: In a multiprocessor system, with conflict checking implemented in a directory lookup of a shared cache memory, a reader set encoding permits dynamic recordation of read accesses. The reader set encoding includes an indication of a portion of a line read, for instance by indicating boundaries of read accesses. Different encodings may apply to different types of speculative execution.

Abstract: A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory.

Abstract: A method of managing memory may include selecting an object of a memory heap to be de-allocated and initiating a deferred lock configured to delay de-allocation of the object. The deferred lock may be acquired in response to a thread leaving a computing space, and the object may be de-allocated.

Abstract: Information is maintained on strides configured in a second cache and occupancy counts for the strides indicating an extent to which the strides are populated with valid tracks and invalid tracks. A determination is made of tracks to demote from a first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are to a second stride in the second cache having an occupancy count indicating the stride is empty. A determination is made of a target stride in the second cache based on the occupancy counts of the strides in the second cache. A determination is made of at least two source strides in the second cache having valid tracks based on the occupancy counts of the strides in the second cache. The target stride is populated with the valid tracks from the source strides.

Abstract: Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not including valid data. A determination is made of tracks to demote from the first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are added to a second stride in the second cache that has no valid tracks. A target stride in the second cache is selected based on a stride most recently used to consolidate strides from at least two strides into one stride. Data from the valid tracks is copied from at least two source strides in the second cache to the target stride.

Abstract: Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not including valid data. A determination is made of tracks to demote from the first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are added to a second stride in the second cache that has no valid tracks. A target stride in the second cache is selected based on a stride most recently used to consolidate strides from at least two strides into one stride. Data from the valid tracks is copied from at least two source strides in the second cache to the target stride.

Abstract: Information is maintained on strides configured in a second cache and occupancy counts for the strides indicating an extent to which the strides are populated with valid tracks and invalid tracks. A determination is made of tracks to demote from a first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are to a second stride in the second cache having an occupancy count indicating the stride is empty. A determination is made of a target stride in the second cache based on the occupancy counts of the strides in the second cache. A determination is made of at least two source strides in the second cache having valid tracks based on the occupancy counts of the strides in the second cache. The target stride is populated with the valid tracks from the source strides.

Abstract: A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions. The first memory allocator is configured to handle a first memory request size distribution. The second memory allocator is configured to handle a second memory request size distribution. The second memory request size distribution is different than the first memory request size distribution. At least the first memory allocator and the second memory allocator that have been configured are deployed within the computing system in support of at least one application. Deploying at least the first memory allocator and the second memory allocator within the computing system improves at least one of performance and memory utilization of the at least one application.

Abstract: Systems and methods allow access between a software application residing within a processor module and an accelerator module having an accelerator address space distinct from the processor address space. Access to the accelerator is provided by mapping the accelerator address space to an associated portion of the processor address space. The association may be made based upon a description of the accelerator address space provided in a pre-determined format. The formatted description is processed to create a software indicator module that is provided to the user application to thereby indicate the associated portion of the processor address space. Access to the associated portion of the processor address space by the software program is redirected to the accelerator address space to thereby allow the application to access the accelerator. A functional interface that allows the software application to issue commands and perform other administrative functions on the accelerator module may also be provided.

Abstract: A storage apparatus includes a written state bit map memory that stores a written state bit map that includes bits each allocated to one of partial areas of a storage device for storing write management information indicating whether written data is present in a partial area of the storage device that is allocated to one of the bits, a bit map management section, when data is written into a partial area of the storage device in response to a write request from the host apparatus, that sets a value indicating that the data is written into the partial area to a bit allocated to the partial area in which the data is written, and a patrolling process section for performing a patrolling process on the partial areas of the storage device on the basis of the write management information stored in the written state bit map memory.