Abstract: A method of making a vertical integrated circuit by providing first and second substrates surfaces of which have layers with circuit structures and metallization planes therein, by providing an etching mask on a primary surface of the first substrate, forming via holes in the first substrate extending through the masking surface and the layers of the first substrate, reducing the thickness of the first substrate from a surface opposite its layer surface, alignedly connecting the first substrate by its reduced surface to the layer surface of the second substrate, subsequent deepening of the via holes to the metallization plane of the second substrate and forming electrical interconnection between the metallization planes in the first and second substrates through the via holes.

Abstract: A method of manufacturing a device which starts with a support bar with a first main surface provided with a groove suitable for accommodating a semiconductor element. The groove has walls on which conductor tracks are provided which continue over the first main surface. This method is particularly suitable for making support bars which serve as envelopes for semiconductor elements. The conductor tracks are provided through patterning of a conductive material by means of a patterned photoresist which is provided on the support bar and irradiated from two directions, at such an angle to the first main surface and to the groove that the bottom of the groove is not irradiated, whereas portions of the walls and of the first main surface are irradiated, after which the photoresist and an applied layer of conductive material are brought into a pattern. This method is more reliable than the known method. In the new method, the geometry of the support bar is used for irradiating the photoresist.

Abstract: A titanium layer is formed by depositing titanium over entire surface of a gate electrode, a P-type silicon substrate, an insulation layer, an oxide layer and so forth. By effecting first RTA (Rapid Thermal Annealing) under nitrogen atmosphere, titanium silicide layer of C49 type structure is formed. At this time, the regions of the titanium layer which are on the oxide layer and the insulation layer and upper part of the region of the titanium layer which is formed on the silicon substrate are reacted with N.sub.2 gas to produce titanium nitride layer. In conjunction therewith, titanium layer on the surface of the insulation layer and the oxide layer is slightly reacted to form titanium silicide thin film. Subsequently, only titanium nitride is selectively removed. Thereafter, under oxygen atmosphere, second RTA is performed at 850.degree. C. for 10 sec. to oxidize the titanium silicide thin film to make it insulative.

Abstract: A process for forming metal composites, using a titanium underlay as part of the composite, with reduced risk of titanium adhesion loss or lifting, has been developed. Several solutions, resulting in protective layers being formed on the exposed titanium sidewall, have been shown. One solution features the addition of nitrogen, as part of reactive ion etching chemistry, during the patterning of the underlying titanium layer. The resulting titanium nitride formation, on the exposed titanium sidewall, protects against subsequent processing steps that may degrade the adhesion of titanium to an underlying material. A second solution describes the formation of a titanium oxide film on the exposed titanium sidewall. This formation occurs during a photoresist plasma strip, using an oxygen-stream ambient. The titanium oxide film again results in protection of the titanium interface, during subsequent processing steps.

Abstract: A method for printing a solder paste to a printed circuit board with use of a screen mask plate and a squeegee, the method includes steps of moving one of the printed circuit board and the screen mask plate at a first moving speed in a direction to be separated from the other of them after printing of the solder paste and until the moving one of the printed circuit board and the screen mask plate reaches a plate-separation position which is a position immediately before the screen mask plate and the printed circuit board are completely separated from each other, and changing the first moving speed to a second moving speed higher than the first moving speed when the moving one of the printed circuit board and the screen mask plate reaches the plate-separation position.

Abstract: A method for forming an interconnect for establishing a temporary electrical connection with contact locations (e.g., bond pads) on a semiconductor die is provided. The interconnect includes a substrate (e.g., silicon) having raised contact members that correspond to the contact locations on the die. Each raised contact member includes one or more projections adapted to penetrate the contact locations on the die to a limited penetration depth. The raised contact member and projections are covered with a metal silicide layer formed using a salicide process. The metal silicide layer is in contact with conductive traces formed on the substrate of a highly conductive metal. Alternately the raised contact members and projections can be formed as a metal layer or as a bi-metal stack.

Abstract: A method of manufacturing semiconductor devices in which a multi-series lead frame that is constructed so as to assemble semiconductor elements in a state that these elements are arrayed in a plurality of series along the longer sides of the lead frame, is set in a mold, and molding resin is injected into cavities of the mold, to thereby form packages for packing the semiconductor elements in a sealing manner. In the method, a resin tablet is positioned so that resin paths are extended at substantially equal lengths to the cavities on the lead frame set in the mold, and the molding resin is injected into the cavities disposed around the resin tablet by pressing the resin tablet with a plunger.

Abstract: A micro-dimensional coupling conductor with a shape that is customized for a particular electronic device. A fabrication method is used in which the physical dimensions of the conductor are precisely controlled with photolithographic techniques, resulting in a conductor that is more precisely tuned to the operating frequency of the device. The conductor is fabricated on an SiO.sub.2 substrate using vacuum deposition or electroplating techniques. After fabrication, the conductor is separated from the SiO.sub.2 substrate by dissolving the SiO.sub.2. Alternatively, the conductor may be fabricated on a Teflon.TM. substrate. The use of a Teflon substrate allows a user to remove the conductor from the substrate by applying a small mechanical force to the conductor.

Abstract: A method for forming a via in an integrated circuit having a reduced contact resistance. The integrated circuit includes a photoresist layer, an oxide layer, an etch stop layer and a metal layer. In one embodiment, a portion of the photoresist layer is removed to expose the underlying oxide layer, after which a portion of the oxide layer is removed to expose the underlying etch stop layer. A portion of the etch stop layer is then removed using a reactive ion etch-downstream microwave ash system under conditions that are effective to create a substantially water-soluble polymer residue within the via, to expose a portion of the underlying metal layer. The water-soluble polymer is then removed to expose the underlying metal layer.

Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.

Abstract: A method for fabricating a diffusion barrier metal layer of a semiconductor device for preventing a material of a metal wiring of said semiconductor device from being diffused into a silicon layer under said metal wiring is disclosed including the steps of: exposing the surface of said silicon layer to oxygen plasma, to prevent a silicide from being formed at the interface between said silicon layer and diffusion barrier metal layer; forming a first diffusion barrier metal layer on said silicon layer; implanting oxygen ions into said first diffusion barrier metal layer; and forming a second diffusion barrier metal layer on said first diffusion barrier metal layer.

Abstract: The method of manufacturing a semiconductor device, according to the present invention, includes the steps of forming a polycrystal lower-level Al wiring layer on a silicon substrate, forming an interlayer insulation film for covering the lower-level Al wiring layer on the entire surface, forming a connection hole which reaches the lower-level Al wiring layer in the interlayer insulation film, forming a polycrystal upper-level Al wiring layer on a surface of the interlayer insulation film, forming an interlayer insulation film for covering the upper-level Al wiring layer on the entire surface, and forming a single-crystal lower-level Al wiring layer and upper-layer Al wiring layer which are connected to each other in the connection hole by heating the silicon substrate so that the lower-level Al wiring layer and the upper-level Al wiring layer are converted from a polycrystal phase to an amorphous phase, and then cooling the silicon substrate so that the upper-level Al wiring layer is set in a supercooling st