Abstract: A method for fabricating a wafer includes providing a wafer table, wherein the wafer table includes support pins that are movable with respect to each other; identifying features of a layer to be formed on a wafer, wherein the features have a tolerance for overlay errors below a threshold; moving one or more support pins based on the features; after the moving of the one or more support pins, mounting the wafer on the wafer table; and after the mounting of the wafer on the wafer table, forming the layer on the wafer.

Abstract: An LED pixel device is disclosed. The LED pixel device includes a first light-transmitting substrate, a second light-transmitting substrate overlying the first light-transmitting substrate, a third light-transmitting substrate overlying the second light-transmitting substrate, a first light-emitting cell underlying the first light-transmitting substrate, a second light-emitting cell interposed between the first light-transmitting substrate and the second light-transmitting substrate, and a third light-emitting cell interposed between the second light-transmitting substrate and the third light-transmitting substrate. The first light-emitting cell, the second light-emitting cell, and the third light-emitting cell emit light of different wavelengths.

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

Abstract: A light-emitting diode includes an N-type cladding layer, and a superlattice structure, an active layer, a P-type electron-blocking layer, and a P-type cladding layer disposed on the N-type cladding layer in such order. The superlattice structure includes at least one first layered element which has first, second, and third sub-layers that are stacked on one another in a direction away from the N-type cladding layer. The first, second, and third sub-layers have energy band gaps Eg1, Eg2, and Eg3 which satisfy a relationship of Eg1<Eg2<Eg3. In addition, Eg3 is greater than an energy band gap of the P-type electron-blocking layer.

Abstract: The present disclosure provides a fan-out antenna packaging structure for a semiconductor chip and its fabricating method. The structure is a stacked-up two sets of metal connecting columns and antenna metal patterns arranged in two sequential layers of packaging materials. In some applications there can be more than two sets of the stacked-up antenna structures, fabricated around the chip at one side of a rewiring layer. The chip is interconnected to external metal bumps on the other side of the rewiring layer.

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor and a second insulator over a first insulator; a third insulator over the first conductor and the second insulator; a fourth insulator over the third insulator; a first oxide over the fourth insulator; a second oxide and a third oxide over the first oxide; a second conductor in contact with a top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the second oxide, and a top surface of the second oxide; a third conductor in contact with the top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the third oxide, and a top surface of the third oxide; a fourth oxide over the first oxide; a fifth insulator over the fourth oxide; and a fourth conductor over the fifth insulator.

Abstract: A method of assembling a DC-DC converter includes: attaching first and second discrete power stage transistor dies to a first side of a substrate, the first discrete die including a high-side power transistor and the second discrete die including a low-side power transistor electrically connected to the high-side power transistor to form an output phase of the DC-DC converter; attaching an inductor to the first side of the substrate so as to electrically connect the output phase to a metal output trace on the substrate, the inductor partly covering at least one of the first and the second discrete power stage transistor dies such that each discrete power stage transistor die that is partly covered by the inductor comprises a plurality of pins that are not covered by the inductor; and visually inspecting the plurality of pins uncovered by the inductor.

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Abstract: A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.

Abstract: A semiconductor device includes a substrate and a light collimator layer. The substrate has a plurality of pixels. The light collimator layer is disposed on the substrate. The light collimator layer includes a light shielding layer disposed on the substrate, a plurality of transparent pillars disposed in the light shielding layer, and a plurality of optical microlenses disposed on the pixels.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.

Abstract: A static random access memory (SRAM) cell has first to sixth transistors that are vertical nanowire (VNW) FETs. The second and fifth transistors are placed side by side sequentially on one side in the X direction of the first transistor. The fourth and sixth transistors are placed side by side sequentially on the other side in the X direction of the third transistor. The first and third transistors are placed side by side in the Y direction.

Abstract: Provided are a method of manufacturing a display apparatus and the display apparatus. The method includes forming an emissive layer and a driving layer on a first area of a substrate, forming an exposure line electrically connected to the driving layer, on a second area of the substrate, and forming a color conversion layer on the driving layer by emitting light from the emissive layer using the exposure line.

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first fin structure and a second fin structure. The method further includes replacing the second fin structure with a third fin structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first fin structure and the second sacrificial layers in the third fin structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first fin structure and each of the second semiconductor layers in the third fin structure, respectively.

Abstract: A semiconductor apparatus according to the invention of the present application includes a base plate, a lead frame having a first surface and a second surface being a surface opposite to the first surface, the second surface being bonded to an upper surface of the base plate, a semiconductor device provided on the first surface of the lead frame, and a mold resin covering the upper surface of the base plate, the lead frame, and the semiconductor device, wherein the mold resin is provided with a terminal insertion hole that extends from the surface of the mold resin to the lead frame and in which a press-fit terminal is inserted, and the lead frame is provided with an opening portion which intercommunicates with the terminal insertion hole and into which the press-fit terminal is press-fitted.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

Abstract: A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region.

Abstract: A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5×1012 ions/cm3 to about 5×1013 ions/cm3, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.

Abstract: A construction of integrated circuitry comprises a horizontal longitudinally-elongated conductive line. A horizontal longitudinally-elongated void space extends longitudinally along opposing longitudinal sides of the conductive line. The void space along each of the opposing longitudinal sides has cyclically varying height longitudinally along the conductive line. Methods independent of the above structure are disclosed.