Patents Examined by Khanh Cong Tran
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Patent number: 6760391Abstract: A method and communications device for controlling the line rate used on a communications link. The method includes receiving frames of digital information, computing a measure of the number of frames received in error in a sliding time window and generating a command to change the line rate as a function of the measure. The use of a sliding time window captures variations in the line quality over an extended period of time; thus, significant disturbances which might otherwise be missed are captured. The measure of the number of frames received in error is computed by applying a many-to-one mapping to the actual number of frame errors received since a previous sampling instant; thus, insignificant short-term disturbances which might otherwise temporarily corrupt the line quality estimate are eliminated.Type: GrantFiled: September 14, 1999Date of Patent: July 6, 2004Assignee: Nortel Networks LimitedInventors: Cristian Alb, Jerzy Matuszewski, Thomas P. Taylor, Michael J. Slonosky
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Patent number: 6754288Abstract: A receiver which may be an xDSL receiver has improved dynamic range. The receiver has a first amplifier, a network of four impedances and a variable gain second amplifier. The variable gain second amplifier has an input connected to an ouput of the first amplifier, an output connected to the first amplifier, and a variable gain control input. The gain of the variable gain second amplifier is 1 K , and the pass-band gain of the receiver is K. By controlling the gain of the receiver with an AGC (automatic gain control), the receiver can amplify and filter inputs over a wide dynamic range with lower distortion and without saturation. Alternatively, the gain of the variable gain second amplifier is - 1 K . The four impedances can be arranged to realise low-pass or high-pass filters.Type: GrantFiled: December 26, 2000Date of Patent: June 22, 2004Assignee: Nortel Networks LimitedInventor: Dan V. Gorcea
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Patent number: 6751276Abstract: A method of decoding a digital signal includes processing the digital using a delay operation in accordance with a frequency characteristic of 1+D, where D is an output signal of the delay element. The processed digital signal is then converted to a three level conversion signal (0, positive, negative). The conversion signal is then processed in accordance with a frequency of 1/(1+D) to generate a decoded signal. The conversion signal is also checked to determine if there is a conversion error. If a conversion error is detected, propagation of the error is restricted, such that a correct decoded signal is provided.Type: GrantFiled: March 27, 2000Date of Patent: June 15, 2004Assignee: Fujitsu LimitedInventors: Koji Okada, Masao Iijima
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Patent number: 6738418Abstract: An xDSL modem having an adaptively adjustable guard band comprising a finite number of spaced-apart frequency bins between the upstream and downstream frequencies. The guard band is adjusted by selecting one from among a plurality of filters belonging to a filter bank of the receiver circuitry. A weighted loss in data capacity is calculated when each of the candidate filters are used, and the filter which gives the lowest loss in data capacity, subject to certain criteria, is used. The adjustment is made pursuant to noise and signal characteristics measured during start or restart of an xDSL communications session.Type: GrantFiled: April 3, 2000Date of Patent: May 18, 2004Assignee: Virata CorporationInventors: James J. Stiscia, Raymond Chen
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Patent number: 6731682Abstract: An equalizer applies a window function to input blocks of data. A first finite filter multiplies each of the windowed input blocks of data with a first set of finite filter coefficients to provide respective first adjusted output blocks of data. This multiplication does not result in a full solution to ghosts. A second finite filter multiplies each of the windowed input blocks of data with a second set of finite filter coefficients to provide respective second adjusted output blocks of data. This multiplication also does not result in a full solution to ghosts. An adder performs an addition based upon corresponding ones of the first and second adjusted output blocks of data. A controller controls the window function and the first and second sets of equalizer coefficients so that, as a result of the addition, a substantially full solution to ghosts is obtained.Type: GrantFiled: April 7, 2000Date of Patent: May 4, 2004Assignee: Zenith Electronics CorporationInventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia
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Patent number: 6731678Abstract: A system and method for extending the operating range and/or increasing the bandwidth of a communication link. The communication link may consist of any two communication devices that are connected by two or more separate “band limited” communication paths for the transmission of information therebetween. In operation, the communication devices use a “frequency split scheme” to divide the information transmitted between the devices into two or more signals, each of which is transmitted over one of the communication paths. A “frequency foldback scheme” may also be used to shift the information from the higher frequencies to the lower frequencies of each respective signal, thereby taking advantage of the fact that more information can be carried in the lower frequencies.Type: GrantFiled: October 30, 2000Date of Patent: May 4, 2004Assignee: Sprint Communications Company, L.P.Inventors: Albert L. White, Martin J. Kaplan
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Patent number: 6731693Abstract: A system for and method of overcoming third order modulation distortion in which a baseband signal is predistorted using one or more parameters configured to reduce or eliminate the third order modulation distortion.Type: GrantFiled: February 29, 2000Date of Patent: May 4, 2004Assignee: Skyworks Solutions, Inc.Inventor: Morten Damgaard
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Patent number: 6731698Abstract: When a clock reproduction circuit (6) is locked, a phase comparator (9) detects a level difference &Dgr;E between a zero crossing point and a true 0 level. The level difference &Dgr;E represents an offset level and is output as an offset detection signal. After being planarized in the LPF (12), the level difference &Dgr;E is input to adders (14) and (15) so as to cancel a DC offset.Type: GrantFiled: March 23, 2000Date of Patent: May 4, 2004Assignee: Sanyo Electric Co., Ltd.Inventor: Kazuaki Yoshie
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Patent number: 6724813Abstract: In a communications system, communications resources are allocated in a dynamic, “as needed” fashion. No explicit signaling is needed to exchange information pertaining specifically to an allocated communications resource. Instead, resources are implicitly allocated by using one or more parameters known to both the radio access network and mobile station that are more or less unique to the mobile station. Such parameters are used to generate or address a communications resource for use by the mobile station. The parameters might, for example, be information readily acquired or communicated as a result of a synchronization procedure, a mobile station registration procedure, a mobile station access procedure, a paging procedure, etc.Type: GrantFiled: October 14, 1998Date of Patent: April 20, 2004Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Karim Jamal, Paul P. Butovitsch, Erik B. L. Dahlman, Riaz Esmailzadeh, Per Willars
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Patent number: 6721351Abstract: An apparatus for producing a plurality of pilot signals corresponding to a multi-frequency assignment (FA) of a small-capacity base transceiver station supporting only the primary frequency assignment (FA1) to perform a hand-off in a CDMA communication system which supports the multi-frequency assignment (FA). The apparatus includes a first phase locked loop (PLL) synthesizer having a first PLL for synthesizing the primary frequency assignment (FA1) signal by controlling the first PLL, a second PLL synthesizer having a second PLL for synthesizing the multi-frequency assignment (FA) signals by controlling the second PLL, and an up-converter for modulating the transmission data with the primary frequency assignment signal provided from the first PLL synthesizer and producing the pilot signals corresponding to the multi-frequency assignment by modulating a signal, prior to RF modulation, with the multi-frequency assignment signals provided from the second PLL synthesizer.Type: GrantFiled: March 15, 2000Date of Patent: April 13, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Sung Lee, Hye-Ki Oh
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Patent number: 6721372Abstract: A method and apparatus to perform a real-time drift correction of a local oscillator in a wireless device such as a cordless telephone, and/or to perform software-based frequency tracking of the local oscillator. With respect to the real-time drift correction, the remote handset periodically wakes from a sleep mode and goes into a normal link verification mode. Once in the link verification mode, the remote handset enters a time division duplexing (TDD) mode and attempts to establish a link with a base unit based on the timing of the TDD data frame. After the remote handset establishes a link with the base unit, the remote handset requests a security word from the base unit. Upon receiving the requested security word, the remote handset determines if the requested security word matches a security word of the remote handset. The remote handset implements a software frequency adjustment of its local oscillator.Type: GrantFiled: March 17, 2000Date of Patent: April 13, 2004Assignee: Lucent Technologies Inc.Inventors: Somnath Banik, Jeffrey P. Grundvig, Richard L. McDowell, Carl R. Stevenson
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Patent number: 6721371Abstract: A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory.Type: GrantFiled: January 5, 2000Date of Patent: April 13, 2004Assignee: L-3 Communications CorporationInventors: Steven T Barham, Zachary C Bagley, Lyman D Horne
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Method and apparatus for signal to noise power ratio estimation in a multi sub-channel CDMA receiver
Patent number: 6717976Abstract: The present invention provides a method and apparatus for regulating the transmission power of a transmitter generating a CDMA signal. The CDMA signal is transported over a main channel which includes a plurality of sub-channels, each sub-channel associated with a particular sub-signal of the CDMA signal. The apparatus includes primarily an SNR estimator functional bloc and a logical functional bloc. The SNR estimator functional block receives as input the sub-signals and is responsible for commuting an estimate of the ratio of the total signal energy in the sub-signals to the total noise energy in the sub-signals. The logical functional bloc generates a control signal in dependence of the SNR estimation computed by the SNR estimation functional bloc. This control signal is sent back to the transmitter generating the CDMA signal, and is indicative of either a power-up or power-down command for regulating the transmission power of the transmitter.Type: GrantFiled: December 21, 1998Date of Patent: April 6, 2004Assignee: Nortel Networks Ltd.Inventor: Qiang Shen -
Patent number: 6717996Abstract: Definition takes place of a sliding window of width Ne times the sampling period (Te); for each sliding window calculation takes place of the sum of the elementary powers of the correlation samples located in said window; determination takes place of the window for which the sum of the powers is at a maximum, the synchronization then being defined by the position of the synchronized window on the window having the maximum power sum and by the rank of each correlation sample within said window.Type: GrantFiled: March 23, 2000Date of Patent: April 6, 2004Assignee: France TelecomInventors: Philippe Du Reau, Daniel Duponteil, Julie Yuan-Wu
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Patent number: 6704377Abstract: The present invention provides a receiver for correcting frequency errors in a receiver of a coherently demodulated communication system, whereby two simultaneous counts are performed for a plurality of symbol comprising an incoming packet of information. In particular, a first count is performed where a counter increases or decreases based on the comparison of symbol phases from outputs of two components of the receiver. Simultaneously, a second counter increments sequentially for each symbol processed. A frequency increment or correction is applied when the first counter reaches a threshold, resetting the first and second counters for subsequent symbols. The receiver may reduce frequency offset estimation errors which degrade channel performance, as compared to algorithms currently utilized to correct frequency errors in wireless communications networks and/or systems. Moreover, a significant improvement in packet error rate may be attainable in accordance with the aforementioned receiver.Type: GrantFiled: March 10, 2000Date of Patent: March 9, 2004Assignee: Lucent Technologies Inc.Inventor: Yi Hsuan
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Patent number: 6700937Abstract: This invention provides an iterative process to maximum a posteriori (MAP) decoding. The iterative process uses an auxiliary function which is defined in terms of a complete data probability distribution. The auxiliary function is derived based on an expectation maximization (EM) algorithm. For a special case of trellis coded modulators, the auxiliary function may be iteratively evaluated by a combination of forward-backward and Viterbi algorithms. The iterative process converges monotonically and thus improves the performance of any decoding algorithm. The MAP decoding minimizes a probability of error. A direct approach to achieve this minimization results in complexity which grows exponentially with T, where T is the size of the input. The iterative process avoids this complexity by converging on the MAP solution through repeated maximization of the auxiliary function.Type: GrantFiled: April 13, 2000Date of Patent: March 2, 2004Assignee: AT&T Corp.Inventor: William Turin
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Patent number: 6700921Abstract: A spread-spectrum communication apparatus includes an analog modulator and demodulator for modulating and demodulating information in its transmitter and receiver respectively. The apparatus also includes a spreader and de-spreader for modulating and demodulating a spread-spectrum signal respectively in its transmitter and receiver. This structure widens a dynamic range of the RSSI with an inexpensive and simple circuit. This structure also allows the apparatus to operate in a stable manner against an intense input signal, to detect an “out of sync” in a highly reliable manner and move immediately to a “sync-tracking mode”.Type: GrantFiled: January 7, 2000Date of Patent: March 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Akira Shibuta
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Patent number: 6693969Abstract: Phase-locked loop methods and structures are provided for generating modulated communication signals with nonconstant envelopes. These methods and structures realize the improved communication performance of nonconstant-envelope modulations with the upconversion advantages of phase-locked loops. The structures include transmitters in which a phase-locked loop is augmented with first and second feedforward paths that substantially restore phase and amplitude information to a transmit signal that is generated by a voltage-controlled oscillator of the phase-locked loop. The first feedforward path is configured to realize a path transfer function of s/Kv wherein the voltage-controlled oscillator has a transfer function of Kv/s. The second feedforward path extracts an envelope-correction signal from the modulated intermediate-frequency signal and a variable-gain output amplifier amplifies the transmit signal with a gain that responds to the envelope-correction signal.Type: GrantFiled: October 11, 2000Date of Patent: February 17, 2004Assignee: Analog Devices, Inc.Inventors: Antonio J. Montalvo, Simon Atkinson
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Patent number: 6687308Abstract: The display section 35 connected to a control section 31 displays, at the same time, both the contents described in the network information table of the digital broadcast data demodulated by a demodulator 42 and complying with the first network, and also the contents described in the network information table of the digital broadcast data replaced by an NIT-replacing circuit 48 and complying with the second network. An NIT-detecting circuit 44 detects an NITa from an MPEG2 transport packet, i.e., digital broadcast data in the satellite broadcasting system (first network). The control section 31 complying with a CATV system (second network) generates the data representing at least the transmission frequency of the NITa detected by the NIT-detecting circuit 44. The NIT-replacing circuit 48 replaces the NITa contained in the MPEG2 transport packet, i.e.Type: GrantFiled: August 31, 2000Date of Patent: February 3, 2004Assignee: Sony CorporationInventors: Kenji Inose, Katsumi Oishi
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Patent number: 6680980Abstract: A Viterbi trellis is provided which allows for implementation of either an EPRML type channel or an E2PRML type channel using a single trellis structure. According to a specific embodiment, a trellis is provided which can support a 0 mod 2 EPRML (M2EPRML) channel and a modified E2PRML (ME2PRML) channel.Type: GrantFiled: February 14, 2000Date of Patent: January 20, 2004Assignee: Infineon Technologies North America Corp.Inventors: Jonathan Ashley, Razmik Karabed