Patents Examined by Khiem V Nguyen
  • Bias control for stacked transistor configuration
    Patent number: 9716477
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 25, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Poojan Wagh, Joseph Golat, David Kovac, Jeffrey A. Dykstra, Chris Olson