Abstract: In an apparatus for processing input N-bit digital video data with an error correction parity, the input N-bit digital video data includes each one sample of higher-order-N-bit data and a plurality of samples of lower-order-(M-N)-bit data, wherein M>N. An error correction circuit corrects an error of input N-bit digital video data, outputs error-corrected N-bit digital video data, and generates an error detection signal representing an error which can not be corrected. Further, a data combining circuit converts the error-corrected N-bit digital video data into M-bit digital video data, and an error classifying circuit classifies the error detection signal into a first error detection signal representing an error of the each one sample of the higher-order-N-bit data and a second error detection signal representing an error of the plurality of samples of the lower-order-(M-N)-bit data.

Abstract: A color signal reproducing circuit comprising a phase correction device receiving a gain-controlled composite color signal, detecting color burst signal in a composite color signal and correcting phase of the color burst signal by using a 3.58 MHz signal, first gate for receiving the gain-controlled composite color signal and passing only a color signal when a color burst pulse in the delayed horizontal synchronizing signal applied from the delay device is at a low level, and mixer for mixing the phase-corrected color burst signal and the color signal from the first gate to produce a phase-corrected composite color signal.