Patents Examined by Kibrom Gebresilassie
-
Patent number: 8145462Abstract: A system and method for optimizing the performance of a drilling device utilizes well logs and drilling parameters from multiple offset wells located in proximity to the location of a desired wellbore. The well logs and drilling parameters data from the offset wells is synthesized to determine major drilling contexts including both geological trends, mechanical properties and the different well profiles. The performance of one or more drilling devices and or drilling parameters is then simulated within the selected drilling contexts of the offset wells. The simulation information is then used to select an optimized drilling device or parameter for drilling the selected wellbore.Type: GrantFiled: April 15, 2005Date of Patent: March 27, 2012Assignee: Halliburton Energy Services, Inc.Inventor: Hubert Foucault
-
Patent number: 8135567Abstract: A method is provided of emulating and visualizing machine tool behavior for a programmable logic controller logical verification system for manufacturing a motor vehicle. The method includes the steps of constructing a mechanical model. The method also includes the steps of viewing motion of the mechanical model in a motion viewer and determining whether the motion of the mechanical model is acceptable. The method further includes the steps of replicating the motion previously defined with PLC code if the motion of the mechanical model was acceptable and using the accepted motion of the mechanical model to compare the behavior of the PLC code relative to the accepted motion.Type: GrantFiled: September 28, 2001Date of Patent: March 13, 2012Assignee: Ford Global Technologies, LLCInventors: Joseph G. Walacavage, Jim D. Coburn
-
Patent number: 8131535Abstract: In emulation of a target system on a host system one or more blocks of target system code may be translated with the host system to produce one or more corresponding blocks of translated code. Translating the target system code may include linking two or more blocks of translated code together to form a chain such that a look-up in a first translated block in the chain will directly branch to a second translated block. The target system code may be analyzed for the presence of one or more native target system instructions indicating modification of the target system code during execution. If such native target system instructions are present some or all of the blocks of translated code may be marked potentially invalid. The one or more blocks marked as potentially invalid may be re-translated and one or more instructions in the blocks of translated code may be overridden without undoing the chain.Type: GrantFiled: June 3, 2011Date of Patent: March 6, 2012Assignee: Sony Computer Entertainment Inc.Inventors: Stewart Sargaison, Victor Suba
-
Patent number: 8131524Abstract: An interface is provided by creating prompts for the interface. The prompts represent tasks to be accomplished by a user and are obtained based on user input. The prompts are grouped according to relationships, obtained from the user input, among the tasks. The interface is updated based on user feedback. Each of the prompts is designated using user terminology obtained from the user input.Type: GrantFiled: May 27, 2008Date of Patent: March 6, 2012Assignee: AT&T Intellectual Property I, L.P.Inventors: Robert R. Bushey, Theodore B. Pasquale, Scott H. Mills, John M. Martin, Benjamin A. Knott, Kurt M. Joseph
-
Patent number: 8126689Abstract: The present invention relates generally to methods for designing and optimizing the number, placement, and size of fractures in a subterranean formation and more particularly to methods that account for stress interference from other fractures when designing and optimizing the number, placement, and size of fractures in the subterranean formation. The present invention optimizes the number, placement and size of fractures in a subterranean formation. The present invention determines one or more geomechanical stresses induced by each fracture based on the dimensions and location of each fracture.Type: GrantFiled: December 4, 2003Date of Patent: February 28, 2012Assignee: Halliburton Energy Services, Inc.Inventors: Mohamed Y. Soliman, Loyd E. East, Jr., David Adams
-
Patent number: 8108201Abstract: A native device includes a memory storing a personal computing environment; an interface configured for coupling with a host information processing system; a native function system for performing a native function; and a native function emulator for emulating the native function in the host information processing system. According to another embodiment, a host information processing system includes: an interface for coupling with a native device comprising its user's personal computing environment; a processor configured for operating with the native device when the native device is coupled; and logic for emulating functions of the native device when the native device is coupled.Type: GrantFiled: November 17, 2005Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Mandayam Thondanur Ragnunath, Chandrasekhar Narayanaswami
-
Patent number: 8103497Abstract: A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the event engine to monitor for the events. The device may have an external pin coupled to the event engine. The event engine may monitor a signal on the external pin to detect events external to the device. Alternatively, the device may output a signal on an external pin in response to detecting one of the events.Type: GrantFiled: March 28, 2002Date of Patent: January 24, 2012Assignee: Cypress Semiconductor CorporationInventors: Craig Nemecek, Steve Roe
-
Patent number: 8103485Abstract: A system and a method for computing an estimated state of charge and an estimated cell resistance of an electrochemical cell are provided. The method includes predicting a first cell resistance value indicating a present resistance of the electrochemical cell utilizing a first nonlinear cell model. The method further includes predicting a first state of charge value indicating a present state of charge of the electrochemical cell utilizing a second nonlinear cell model. The method further includes measuring a voltage and, a current associated with the electrochemical cell to obtain a voltage value and a current value, respectively. The method further includes estimating a second state of charge value indicating the present state of charge of the electrochemical cell utilizing the second nonlinear cell model based on the first state of charge value, the first cell resistance value, the voltage value, and the current value.Type: GrantFiled: November 11, 2004Date of Patent: January 24, 2012Assignee: LG Chem, Ltd.Inventor: Gregory L. Plett
-
Patent number: 8095343Abstract: Provided are a method and apparatus for modeling source-drain current of a TFT. The method includes receiving sample data, the sample data including a sample input value and a sample output value; adjusting modeling variables according to the sample data; calculating a current model value according to the adjusted modeling variables; when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model; applying actual input data to the fitted current model; and outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.Type: GrantFiled: August 29, 2008Date of Patent: January 10, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Heon Shin, Chi Sun Hwang, Min Ki Ryu, Woo Seok Cheong, Hye Yong Chu
-
Patent number: 8090565Abstract: In one embodiment, a system model models characteristics of a real-world system. The system model includes a plurality of sub-portions that each correspond to a component of the real-world system. A plurality of test vectors are applied to the system model and coverage achieved by the test vectors on the sub-portions of the system model is measured. In response to a failure of the real world system, a suspected failed component of the real-world system is matched to a particular sub-portion of the system model. A test vector to be applied to the real-world system to test the suspected failed component is selected in response to coverage achieved on the particular sub-portion of the system model.Type: GrantFiled: January 8, 2008Date of Patent: January 3, 2012Assignee: The MathWorks, Inc.Inventor: Thomas Gaudette
-
Patent number: 8073671Abstract: Simulating an application. A method that may be practiced in a computing environment configured for simulating an application modeled by an application model deployed in a performance scenario of a computing system by deploying service models of the application model to device models modeling devices. The method includes referencing a performance scenario to obtain a transaction being modeled as originating from a first device model. The transaction invokes of a first service model. The first service model specifies hardware actions for simulation. The first service model is referenced to determine the hardware actions for simulation and the next referenced service. The next referenced service specifies hardware actions to be added to the transaction and may specify invocation of other service models. A chain of hardware actions is generated by following the invocation path of the service models. The hardware actions are applied to device models to simulate the transaction.Type: GrantFiled: March 31, 2006Date of Patent: December 6, 2011Assignee: Microsoft CorporationInventors: Efstathios Papaefstathiou, John M. Oslake, Jonathan C. Hardwick, Pavel A. Dournov
-
Patent number: 8069020Abstract: A first wafer is fabricated using a first value for a process parameter specifying a process condition in fabricating the structure. A first value of a dispersion is measured from the first wafer. A second wafer is fabricated using a second value for the process parameter. A second value of the dispersion is measured from the second wafer. A third wafer is fabricated using a third value for the process parameter. The first, second, and third values for the process parameter are different from each other. A third value of the dispersion is measured from the third wafer. A dispersion function is defined to relate the process parameter to the dispersion using the first, second, and third values for the process parameter and the measured first, second, and third values of the dispersion. The simulated diffraction signal is generated using the defined dispersion function. The simulated diffraction signal is stored.Type: GrantFiled: September 19, 2007Date of Patent: November 29, 2011Assignee: Tokyo Electron LimitedInventors: Shifang Li, Hanyou Chu
-
Patent number: 8036863Abstract: A method for customizing a bearing bore in a housing so that the bearing assembly will transmit load in a desired manner over a predetermined range of operating temperatures.Type: GrantFiled: January 30, 2009Date of Patent: October 11, 2011Assignee: American Axle & Manufacturing, Inc.Inventors: David P Schankin, Suhui W Wang, Chih-Hung Chung, Zhaohui Sun
-
Patent number: 8032337Abstract: The present invention relates to a method for computer-controlled modelling of customised earpieces. These earpieces include housings for hearing aids, wireless or connected communication devices (headsets, mobile phones, personal agents), loud speakers, tinnitus masking devices, devices recording vibrations in the skull and transforming these into audio signals, voice recognition devices, earplugs, noise blockers with selective frequencies or sound levels, Man Machine Interface (MMI) products that enable clear communication even in the noisiest environments, or products related to wireless Internet applications. All these earpieces may be worn in the user's meatus and/or auditory canal. The invention also relates to a computerised system for manufacturing such customised earpieces. In particular, the invention is directed to a computerised system that models an earpiece based on a three-dimensional replica of the user's meatus and/or auditory canal.Type: GrantFiled: March 1, 2002Date of Patent: October 4, 2011Assignee: 3Shape A/SInventors: Nikolaj Deichmann, Tais Clausen, Rune Fisker, Christophe Vasiljev Barthe
-
Patent number: 8027813Abstract: A system and method of calculating estimated image profiles. The system and method includes providing lens characteristic data and performing simulation calculations for various levels of aberration components using the lens characteristic data. A response surface functional relation is built between selected variables of the lens characteristics, in particular the lens aberration components, and the Image Profile using the simulation calculations. Evaluation is then performed on the arbitrary specified aberration values of a lens in relation to the response surface functional relations to provide a calculated estimate of the Image Profile for the specified aberration values. A machine readable medium and exposure apparatus are also provided.Type: GrantFiled: February 20, 2004Date of Patent: September 27, 2011Assignee: Nikon Precision, Inc.Inventor: Steven Douglas Slonaker
-
Patent number: 8019573Abstract: Drawing conversion assignment and management systems are provided that typically include receiving logic, a database, assignment logic, and completion logic. The receiving logic typically receives notification of completion of a land base drawing file. The database creates a drawing conversion job record associated with the land base drawing file. The assignment logic assigns the drawing conversion job record to a draftsman and instructs the database to record the assignment. The completion logic typically receives a request to close the drawing conversion job record, and instructs the database to mark the drawing conversion job record as closed. Methods and other systems are also provided.Type: GrantFiled: December 5, 2003Date of Patent: September 13, 2011Assignee: AT&T Intellectual Property I, L.P.Inventors: Diane C. Thornton, Michael S. Hess, Rickey Howard Johnson
-
Patent number: 7983880Abstract: Extended linear superposition methods, computer program products and systems to calculate Simultaneous Switching Noise (SSN) on victim Input/Output (I/O) pins of an electronic component caused by aggressor I/O pins is provided. A method includes calculating the quiet output voltage on a victim pin caused by the power supply only, and then calculating an aggressor noise response induced on the victim pin caused by a single aggressor pin and the power supply. To calculate SSN for a combination of aggressors, the SSNs for the different aggressors are linearly combined, and then the effects of the power supply are discounted by using the calculated quiet output voltage. Additionally, a linear victim substitution model is introduced to replace a full buffer model for a victim pin with a resistor with different resistance values depending on the induced voltage. Further, an alternate transmission line model is introduced to simplify SSN simulations of transmission lines.Type: GrantFiled: February 20, 2008Date of Patent: July 19, 2011Assignee: Altera CorporationInventors: Joshua David Fender, Paul Leventis
-
Patent number: 7970594Abstract: A mechanism for exploiting the data gathered about a system model during the system design phase to aid the identification of errors subsequently detected in a deployed system based on the system model is disclosed. The present invention utilizes the coverage analysis from the design phase that is originally created to determine whether the system model as designed meets the specified system requirements. Included in the coverage analysis report is the analysis of which sets of test vectors utilized in simulating the system model excited individual components and sections of the system model. The present invention uses the information associated with the test vectors to select appropriate test vectors to use to perform directed testing of the deployed system so as to confirm a suspected fault.Type: GrantFiled: June 30, 2005Date of Patent: June 28, 2011Assignee: The MathWorks, Inc.Inventor: Thomas Gaudette
-
Patent number: 7957952Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.Type: GrantFiled: August 12, 2010Date of Patent: June 7, 2011Assignee: Sony Computer Entertainment Inc.Inventors: Stewart Sargaison, Victor Suba
-
Patent number: 7933747Abstract: Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.Type: GrantFiled: November 6, 2007Date of Patent: April 26, 2011Assignee: Cadence Design Systems, Inc.Inventors: Yutao Ma, Min-Chie Jeng, Bruce W. McGaughy, Lifeng Wu, Zhihong Liu